| /drivers/net/e1000e/ |
| D | lib.c | 118 hw_dbg(hw, "Programming MAC Address into RAR[0]\n"); in e1000e_init_rx_addrs()
123 hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1); in e1000e_init_rx_addrs()
306 hw_dbg(hw, "Clearing MTA\n"); in e1000e_update_mc_addr_list_generic()
315 hw_dbg(hw, "Hash value = 0x%03X\n", hash_value); in e1000e_update_mc_addr_list_generic()
437 hw_dbg(hw, "Error configuring flow control\n"); in e1000e_check_for_copper_link()
477 hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n"); in e1000e_check_for_fiber_link()
490 hw_dbg(hw, "Error configuring flow control\n"); in e1000e_check_for_fiber_link()
500 hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n"); in e1000e_check_for_fiber_link()
542 hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n"); in e1000e_check_for_serdes_link()
555 hw_dbg(hw, "Error configuring flow control\n"); in e1000e_check_for_serdes_link()
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| D | phy.c | 136 hw_dbg(hw, "PHY Address %d is out of range\n", offset); in e1000e_read_phy_reg_mdic()
163 hw_dbg(hw, "MDI Read did not complete\n"); in e1000e_read_phy_reg_mdic()
167 hw_dbg(hw, "MDI Error\n"); in e1000e_read_phy_reg_mdic()
189 hw_dbg(hw, "PHY Address %d is out of range\n", offset); in e1000e_write_phy_reg_mdic()
217 hw_dbg(hw, "MDI Write did not complete\n"); in e1000e_write_phy_reg_mdic()
221 hw_dbg(hw, "MDI Error\n"); in e1000e_write_phy_reg_mdic()
524 hw_dbg(hw, "Error committing the PHY changes\n"); in e1000e_copper_link_setup_m88()
544 hw_dbg(hw, "Error resetting the PHY.\n"); in e1000e_copper_link_setup_igp()
557 hw_dbg(hw, "Error Disabling LPLU D0\n"); in e1000e_copper_link_setup_igp()
693 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised); in e1000_phy_setup_autoneg()
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| D | ich8lan.c | 297 hw_dbg(hw, "ERROR: Flash registers not mapped\n"); in e1000_init_nvm_params_ich8lan()
435 hw_dbg(hw, "FW or HW has locked the resource for too long.\n"); in e1000_acquire_swflag_ich8lan()
543 hw_dbg(hw, "IFE PMC: %X\n", data); in e1000_phy_force_speed_duplex_ich8lan()
548 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n"); in e1000_phy_force_speed_duplex_ich8lan()
558 hw_dbg(hw, "Link taking longer than expected.\n"); in e1000_phy_force_speed_duplex_ich8lan()
627 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n"); in e1000_phy_hw_reset_ich8lan()
709 hw_dbg(hw, "Phy info is only valid if link is up\n"); in e1000_get_phy_info_ife_ich8lan()
994 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - " in e1000_valid_nvm_bank_detect_ich8lan()
1024 hw_dbg(hw, "ERROR: No valid NVM bank present\n"); in e1000_valid_nvm_bank_detect_ich8lan()
1052 hw_dbg(hw, "nvm parameter(s) out of bounds\n"); in e1000_read_nvm_ich8lan()
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| D | es2lan.c | 402 hw_dbg(hw, in e1000_acquire_swfw_sync_80003es2lan()
605 hw_dbg(hw, "MNG configuration cycle has not completed.\n"); in e1000_get_cfg_done_80003es2lan()
638 hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
656 hw_dbg(hw, "Waiting for forced speed/duplex link " in e1000_phy_force_speed_duplex_80003es2lan()
779 hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_80003es2lan()
781 hw_dbg(hw, "Masking off all interrupts\n"); in e1000_reset_hw_80003es2lan()
793 hw_dbg(hw, "Issuing a global reset to MAC\n"); in e1000_reset_hw_80003es2lan()
828 hw_dbg(hw, "Error initializing identification LED\n"); in e1000_init_hw_80003es2lan()
833 hw_dbg(hw, "Initializing the IEEE VLAN\n"); in e1000_init_hw_80003es2lan()
840 hw_dbg(hw, "Zeroing the MTA\n"); in e1000_init_hw_80003es2lan()
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| D | 82571.c | 425 hw_dbg(hw, "Driver can't access the NVM\n"); in e1000_get_hw_semaphore_82571()
626 hw_dbg(hw, "nvm parameter(s) out of bounds\n"); in e1000_write_nvm_eewr_82571()
667 hw_dbg(hw, "MNG configuration cycle has not completed.\n"); in e1000_get_cfg_done_82571()
766 hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_82571()
768 hw_dbg(hw, "Masking off all interrupts\n"); in e1000_reset_hw_82571()
801 hw_dbg(hw, "Issuing a global reset to MAC\n"); in e1000_reset_hw_82571()
855 hw_dbg(hw, "Error initializing identification LED\n"); in e1000_init_hw_82571()
860 hw_dbg(hw, "Initializing the IEEE VLAN\n"); in e1000_init_hw_82571()
874 hw_dbg(hw, "Zeroing the MTA\n"); in e1000_init_hw_82571()
1219 hw_dbg(hw, "NVM Read Error\n"); in e1000_valid_led_default_82571()
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| D | hw.h | 895 #define hw_dbg(hw, format, arg...) \ macro
899 hw_dbg(struct e1000_hw *hw, const char *format, ...) in hw_dbg() function
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| /drivers/net/igb/ |
| D | e1000_mac.c | 154 hw_dbg("NVM Read Error\n"); in igb_check_alt_mac_addr()
170 hw_dbg("NVM Read Error\n"); in igb_check_alt_mac_addr()
447 hw_dbg("Error configuring flow control\n"); in igb_check_for_copper_link()
485 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type); in igb_setup_link()
498 hw_dbg("Initializing the Flow Control address, type and timer regs\n"); in igb_setup_link()
595 hw_dbg("NVM Read Error\n"); in igb_set_default_fc()
646 hw_dbg("hw->fc.type = %u\n", hw->fc.type); in igb_force_mac_fc()
664 hw_dbg("Flow control param set incorrectly\n"); in igb_force_mac_fc()
707 hw_dbg("Error forcing flow control settings\n"); in igb_config_fc_after_link_up()
733 hw_dbg("Copper PHY and Auto Neg " in igb_config_fc_after_link_up()
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| D | e1000_82575.c | 282 hw_dbg("PHY Address %u is out of range\n", offset); in igb_read_phy_reg_sgmii_82575()
305 hw_dbg("I2CCMD Read did not complete\n"); in igb_read_phy_reg_sgmii_82575()
309 hw_dbg("I2CCMD Error bit set\n"); in igb_read_phy_reg_sgmii_82575()
336 hw_dbg("PHY Address %d is out of range\n", offset); in igb_write_phy_reg_sgmii_82575()
363 hw_dbg("I2CCMD Write did not complete\n"); in igb_write_phy_reg_sgmii_82575()
367 hw_dbg("I2CCMD Error bit set\n"); in igb_write_phy_reg_sgmii_82575()
407 hw_dbg("Vendor ID 0x%08X read at address %u\n", in igb_get_phy_id_82575()
416 hw_dbg("PHY address %u was unreadable\n", phy->addr); in igb_get_phy_id_82575()
448 hw_dbg("Soft resetting SGMII attached PHY...\n"); in igb_phy_hw_reset_sgmii_82575()
616 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); in igb_acquire_swfw_sync_82575()
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| D | e1000_phy.c | 147 hw_dbg("PHY Address %d is out of range\n", offset); in igb_read_phy_reg_mdic()
175 hw_dbg("MDI Read did not complete\n"); in igb_read_phy_reg_mdic()
180 hw_dbg("MDI Error\n"); in igb_read_phy_reg_mdic()
205 hw_dbg("PHY Address %d is out of range\n", offset); in igb_write_phy_reg_mdic()
234 hw_dbg("MDI Write did not complete\n"); in igb_write_phy_reg_mdic()
239 hw_dbg("MDI Error\n"); in igb_write_phy_reg_mdic()
426 hw_dbg("Error committing the PHY changes\n"); in igb_copper_link_setup_m88()
454 hw_dbg("Error resetting the PHY.\n"); in igb_copper_link_setup_igp()
470 hw_dbg("Error Disabling LPLU D3\n"); in igb_copper_link_setup_igp()
478 hw_dbg("Error Disabling LPLU D0\n"); in igb_copper_link_setup_igp()
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| D | e1000_nvm.c | 205 hw_dbg("Could not acquire NVM grant\n"); in igb_acquire_nvm()
340 hw_dbg("SPI NVM Status error\n"); in igb_ready_nvm_eeprom()
371 hw_dbg("nvm parameter(s) out of bounds\n"); in igb_read_nvm_eerd()
417 hw_dbg("nvm parameter(s) out of bounds\n"); in igb_write_nvm_spi()
492 hw_dbg("NVM Read Error\n"); in igb_read_part_num()
499 hw_dbg("NVM Read Error\n"); in igb_read_part_num()
525 hw_dbg("NVM Read Error\n"); in igb_read_mac_addr()
559 hw_dbg("NVM Read Error\n"); in igb_validate_nvm_checksum()
566 hw_dbg("NVM Checksum Invalid\n"); in igb_validate_nvm_checksum()
592 hw_dbg("NVM Read Error while updating checksum.\n"); in igb_update_nvm_checksum()
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| D | e1000_hw.h | 595 #define hw_dbg(format, arg...) \ macro
598 #define hw_dbg(format, arg...) macro
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| /drivers/net/ixgbe/ |
| D | ixgbe_common.c | 214 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_num_generic()
221 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_num_generic()
305 hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); in ixgbe_stop_adapter_generic()
387 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: " in ixgbe_init_eeprom_params_generic()
485 hw_dbg(hw, "Eeprom read timed out\n"); in ixgbe_read_eeprom_generic()
548 hw_dbg(hw, "Could not acquire EEPROM grant\n"); in ixgbe_acquire_eeprom()
621 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " in ixgbe_get_eeprom_semaphore()
681 hw_dbg(hw, "SPI EEPROM Status error\n"); in ixgbe_ready_eeprom()
876 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum()
942 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
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| D | ixgbe_phy.c | 203 hw_dbg(hw, "PHY address command did not complete.\n"); in ixgbe_read_phy_reg_generic()
234 hw_dbg(hw, "PHY read command didn't complete\n"); in ixgbe_read_phy_reg_generic()
303 hw_dbg(hw, "PHY address cmd didn't complete\n"); in ixgbe_write_phy_reg_generic()
334 hw_dbg(hw, "PHY address cmd didn't complete\n"); in ixgbe_write_phy_reg_generic()
465 hw_dbg(hw, "PHY reset did not complete.\n"); in ixgbe_reset_phy_nl()
489 hw_dbg(hw, "DELAY: %d MS\n", edata); in ixgbe_reset_phy_nl()
493 hw_dbg(hw, "DATA: \n"); in ixgbe_reset_phy_nl()
501 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, in ixgbe_reset_phy_nl()
509 hw_dbg(hw, "CONTROL: \n"); in ixgbe_reset_phy_nl()
511 hw_dbg(hw, "EOL\n"); in ixgbe_reset_phy_nl()
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| D | ixgbe_82598.c | 251 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is" in ixgbe_setup_fc_82598()
312 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_setup_fc_82598()
326 hw_dbg(hw, "Flow control structure initialized incorrectly\n"); in ixgbe_setup_fc_82598()
397 hw_dbg(hw, "Autonegotiation did not complete.\n"); in ixgbe_setup_mac_link_82598()
667 hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); in ixgbe_reset_hw_82598()
687 hw_dbg(hw, "Reset polling failed to complete.\n"); in ixgbe_reset_hw_82598()
758 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_clear_vmdq_82598()
975 hw_dbg(hw, "EEPROM read did not pass.\n"); in ixgbe_read_i2c_eeprom_82598()
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| D | ixgbe_common.h | 86 #define hw_dbg(hw, format, arg...) \ macro
90 hw_dbg(struct ixgbe_hw *hw, const char *format, ...) in hw_dbg() function
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