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Searched refs:dpll (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/gma500/
Doaktrail_crtc.c187 temp = REG_READ(map->dpll); in oaktrail_crtc_dpms()
189 REG_WRITE(map->dpll, temp); in oaktrail_crtc_dpms()
190 REG_READ(map->dpll); in oaktrail_crtc_dpms()
193 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in oaktrail_crtc_dpms()
194 REG_READ(map->dpll); in oaktrail_crtc_dpms()
197 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in oaktrail_crtc_dpms()
198 REG_READ(map->dpll); in oaktrail_crtc_dpms()
247 temp = REG_READ(map->dpll); in oaktrail_crtc_dpms()
249 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in oaktrail_crtc_dpms()
250 REG_READ(map->dpll); in oaktrail_crtc_dpms()
[all …]
Dmdfld_intel_display.c294 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
300 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
301 REG_READ(map->dpll); in mdfld_disable_crtc()
308 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
350 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
357 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
362 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
363 REG_READ(map->dpll); in mdfld_crtc_dpms()
367 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
368 REG_READ(map->dpll); in mdfld_crtc_dpms()
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Dpsb_intel_display.c334 temp = REG_READ(map->dpll); in psb_intel_crtc_dpms()
336 REG_WRITE(map->dpll, temp); in psb_intel_crtc_dpms()
337 REG_READ(map->dpll); in psb_intel_crtc_dpms()
340 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in psb_intel_crtc_dpms()
341 REG_READ(map->dpll); in psb_intel_crtc_dpms()
344 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in psb_intel_crtc_dpms()
345 REG_READ(map->dpll); in psb_intel_crtc_dpms()
398 temp = REG_READ(map->dpll); in psb_intel_crtc_dpms()
400 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in psb_intel_crtc_dpms()
401 REG_READ(map->dpll); in psb_intel_crtc_dpms()
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Dmdfld_device.c197 pipe->dpll = PSB_RVDC32(map->dpll); in mdfld_save_display_registers()
251 u32 dpll; in mdfld_restore_display_registers() local
258 u32 dpll_val = pipe->dpll; in mdfld_restore_display_registers()
283 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
284 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
289 dpll = PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
291 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
295 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_restore_display_registers()
296 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_restore_display_registers()
297 PSB_WVDC32(dpll, map->dpll); in mdfld_restore_display_registers()
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Dcdv_intel_display.c889 temp = REG_READ(map->dpll); in cdv_intel_crtc_dpms()
891 REG_WRITE(map->dpll, temp); in cdv_intel_crtc_dpms()
892 REG_READ(map->dpll); in cdv_intel_crtc_dpms()
895 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in cdv_intel_crtc_dpms()
896 REG_READ(map->dpll); in cdv_intel_crtc_dpms()
899 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in cdv_intel_crtc_dpms()
900 REG_READ(map->dpll); in cdv_intel_crtc_dpms()
975 temp = REG_READ(map->dpll); in cdv_intel_crtc_dpms()
977 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in cdv_intel_crtc_dpms()
978 REG_READ(map->dpll); in cdv_intel_crtc_dpms()
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Doaktrail_hdmi.c287 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
297 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
298 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
299 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
313 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
314 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
315 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
319 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
Doaktrail_device.c209 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers()
326 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers()
467 .dpll = MRST_DPLL_A,
491 .dpll = DPLL_B,
Dpsb_device.c307 .dpll = DPLL_A,
331 .dpll = DPLL_B,
Dcdv_device.c567 .dpll = DPLL_A,
592 .dpll = DPLL_B,
Dpsb_drv.h293 u32 dpll; member
329 u32 dpll; member
Dmdfld_dsi_pkg_sender.c638 pkg_sender->dpll_reg = map->dpll; in mdfld_dsi_pkg_sender_init()
/drivers/gpu/drm/i915/
Dintel_display.c3241 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) in intel_get_pch_pll() argument
3272 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && in intel_get_pch_pll()
3302 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); in intel_get_pch_pll()
3307 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); in intel_get_pch_pll()
4174 struct dpll *clock = &crtc->config.dpll; in i9xx_adjust_sdvo_tv_clock()
4202 struct dpll *clock = &crtc->config.dpll; in i9xx_update_pll_dividers()
4241 u32 dpll, mdiv, pdiv; in vlv_update_pll() local
4251 dpll = DPLL_VGA_MODE_DIS; in vlv_update_pll()
4252 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV; in vlv_update_pll()
4253 dpll |= DPLL_REFA_CLK_ENABLE_VLV; in vlv_update_pll()
[all …]
Dintel_drv.h211 struct dpll { struct
215 } dpll; member
/drivers/ata/
Dpata_hpt3x2n.c317 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
324 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
333 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
335 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
337 flags |= dpll; in hpt3x2n_qc_issue()
340 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
Dpata_hpt37x.c983 int dpll, adjust; in hpt37x_init_one() local
986 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
988 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
1016 if (dpll == 3) in hpt37x_init_one()
1022 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/drivers/video/intelfb/
Dintelfbhw.c682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
688 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
695 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
697 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
700 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
701 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1048 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1063 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1075 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
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/drivers/ide/
Dhpt366.c853 u32 dpll = (f_high << 16) | f_low | 0x100; in hpt37x_calibrate_dpll() local
857 pci_write_config_dword(dev, 0x5c, dpll); in hpt37x_calibrate_dpll()
874 pci_read_config_dword (dev, 0x5c, &dpll); in hpt37x_calibrate_dpll()
875 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); in hpt37x_calibrate_dpll()