Searched refs:ir (Results 1 – 25 of 34) sorted by relevance
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76 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir) in mipsr6_emul() argument78 switch (MIPSInst_OPCODE(ir)) { in mipsr6_emul()80 if (MIPSInst_RT(ir)) in mipsr6_emul()81 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()82 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()83 (s32)MIPSInst_SIMM(ir); in mipsr6_emul()89 if (MIPSInst_RT(ir)) in mipsr6_emul()90 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()91 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()92 (s64)MIPSInst_SIMM(ir); in mipsr6_emul()[all …]
195 fpudispatch(u_int ir, u_int excp_code, u_int holder, u_int fpregs[]) in fpudispatch() argument207 class = get_class(ir); in fpudispatch()210 subop = get_subop1_PA2_0(ir); in fpudispatch()212 subop = get_subop1_PA1_1(ir); in fpudispatch()215 subop = get_subop(ir); in fpudispatch()222 return(decode_0c(ir,class,subop,fpregs)); in fpudispatch()224 return(decode_0e(ir,class,subop,fpregs)); in fpudispatch()226 return(decode_06(ir,fpregs)); in fpudispatch()228 return(decode_26(ir,fpregs)); in fpudispatch()230 return(decode_2e(ir,fpregs)); in fpudispatch()[all …]
854 mips_instruction ir) in cop1_cfc() argument859 switch (MIPSInst_RD(ir)) { in cop1_cfc()863 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()873 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()881 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()892 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()903 if (MIPSInst_RT(ir)) in cop1_cfc()904 xcp->regs[MIPSInst_RT(ir)] = value; in cop1_cfc()911 mips_instruction ir) in cop1_ctc() argument917 if (MIPSInst_RT(ir) == 0) in cop1_ctc()[all …]
209 int mips_dsemul(struct pt_regs *regs, mips_instruction ir, in mips_dsemul() argument216 if (ir == 0) in mips_dsemul()221 union mips_instruction insn = { .word = ir }; in mips_dsemul()224 if ((ir >> 16) == MM_NOP16) in mips_dsemul()252 err = __put_user(ir >> 16, (u16 __user *)(&fr->emul)); in mips_dsemul()253 err |= __put_user(ir & 0xffff, (u16 __user *)((long)(&fr->emul) + 2)); in mips_dsemul()257 err = __put_user(ir, &fr->emul); in mips_dsemul()
41 extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
232 __BUILD_MSA_CTL_REG(ir, 0)
57 /* The ir receiver is not always populated */62 ir0: ir@01c21800 {
8 ir_recv: ir-receiver {9 compatible = "gpio-ir-receiver";119 pinctrl_cubox_i_ir: cubox-i-ir {
59 ir_recv: ir-receiver {60 compatible = "gpio-ir-receiver";
61 ir_recv: gpio-ir-receiver {62 compatible = "gpio-ir-receiver";265 ir-receiver {266 ir_recv_pin: ir-recv-pin {
12 ir_recv: ir-receiver {13 compatible = "gpio-ir-receiver";
74 ir0: ir@01c21800 {
654 ir0: ir@01c21800 {655 compatible = "allwinner,sun4i-a10-ir";657 clock-names = "apb", "ir";663 ir1: ir@01c21c00 {664 compatible = "allwinner,sun4i-a10-ir";666 clock-names = "apb", "ir";
69 ir0: ir@01c21800 {
83 ir0: ir@01c21800 {
90 ir0: ir@01c21800 {
91 ir0: ir@01c21800 {
81 ir0: ir@01c21800 {
875 ir0: ir@01c21800 {876 compatible = "allwinner,sun4i-a10-ir";878 clock-names = "apb", "ir";884 ir1: ir@01c21c00 {885 compatible = "allwinner,sun4i-a10-ir";887 clock-names = "apb", "ir";
97 ir0: ir@01c21800 {
103 ir0: ir@01c21800 {
105 ir0: ir@01c21800 {
99 #define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED) argument101 #define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED) argument
46 __be32 ir; member81 return in_be32(®s->ir) & GPIO_MASK(gpio); in ppc4xx_gpio_get()
280 unsigned long ir : 1; member