Home
last modified time | relevance | path

Searched refs:INTEL_INFO (Results 1 – 25 of 32) sorted by relevance

12

/drivers/gpu/drm/i915/
Di915_drv.h86 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
168 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
170 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
171 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
2045 #define INTEL_INFO(p) (&__I915__(p)->info) macro
2046 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2050 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2052 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2055 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2056 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
[all …]
Di915_gem_tiling.c94 if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) { in i915_gem_detect_bit_6_swizzle()
104 } else if (INTEL_INFO(dev)->gen >= 6) { in i915_gem_detect_bit_6_swizzle()
229 if (INTEL_INFO(dev)->gen >= 7) { in i915_tiling_ok()
232 } else if (INTEL_INFO(dev)->gen >= 4) { in i915_tiling_ok()
252 if (INTEL_INFO(dev)->gen >= 4) { in i915_tiling_ok()
274 if (INTEL_INFO(obj->base.dev)->gen >= 4) in i915_gem_object_fence_ok()
277 if (INTEL_INFO(obj->base.dev)->gen == 3) { in i915_gem_object_fence_ok()
Di915_ums.c127 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) in i915_save_display_reg()
165 if (INTEL_INFO(dev)->gen >= 4) { in i915_save_display_reg()
184 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) in i915_save_display_reg()
222 if (INTEL_INFO(dev)->gen >= 4) { in i915_save_display_reg()
230 switch (INTEL_INFO(dev)->gen) { in i915_save_display_reg()
274 if (INTEL_INFO(dev)->gen <= 4) in i915_save_display_reg()
285 if (INTEL_INFO(dev)->gen >= 4) in i915_save_display_reg()
300 if (INTEL_INFO(dev)->gen <= 4) in i915_restore_display_reg()
313 if (INTEL_INFO(dev)->gen >= 4) in i915_restore_display_reg()
331 switch (INTEL_INFO(dev)->gen) { in i915_restore_display_reg()
[all …]
Dintel_ringbuffer.c472 if (INTEL_INFO(ring->dev)->gen >= 8) in intel_ring_get_active_head()
475 else if (INTEL_INFO(ring->dev)->gen >= 4) in intel_ring_get_active_head()
489 if (INTEL_INFO(ring->dev)->gen >= 4) in ring_setup_phys_status_page()
620 if (INTEL_INFO(dev)->gen >= 5) { in intel_fini_pipe_control()
809 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) in init_render_ring()
818 if (INTEL_INFO(dev)->gen >= 6) in init_render_ring()
823 if (INTEL_INFO(dev)->gen == 6) in init_render_ring()
833 if (INTEL_INFO(dev)->gen >= 5) { in init_render_ring()
849 if (INTEL_INFO(dev)->gen >= 6) in init_render_ring()
881 num_rings = hweight32(INTEL_INFO(dev)->ring_mask); in gen8_rcs_signal()
[all …]
Di915_suspend.c197 if (INTEL_INFO(dev)->gen <= 4) in i915_save_display()
240 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) in i915_save_display()
253 if (INTEL_INFO(dev)->gen <= 4) in i915_restore_display()
264 else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) in i915_restore_display()
295 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) in i915_restore_display()
336 if (INTEL_INFO(dev)->gen < 7) in i915_save_state()
386 if (INTEL_INFO(dev)->gen < 7) in i915_restore_state()
Di915_gpu_error.c258 if (INTEL_INFO(dev)->gen >= 4) { in i915_ring_error_state()
266 if (INTEL_INFO(dev)->gen >= 6) { in i915_ring_error_state()
284 if (INTEL_INFO(dev)->gen >= 8) { in i915_ring_error_state()
364 if (INTEL_INFO(dev)->gen >= 8) { in i915_error_state_to_str()
383 if (INTEL_INFO(dev)->gen >= 6) { in i915_error_state_to_str()
388 if (INTEL_INFO(dev)->gen == 7) in i915_error_state_to_str()
767 switch (INTEL_INFO(dev)->gen) { in i915_gem_record_fences()
852 if (INTEL_INFO(dev)->gen >= 6) { in i915_record_ring_state()
855 if (INTEL_INFO(dev)->gen >= 8) in i915_record_ring_state()
861 if (INTEL_INFO(dev)->gen >= 4) { in i915_record_ring_state()
[all …]
Di915_gem_context.c113 switch (INTEL_INFO(dev)->gen) { in get_context_size()
169 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { in i915_gem_alloc_context_obj()
474 hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : in mi_set_context()
490 if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8) in mi_set_context()
495 if (INTEL_INFO(ring->dev)->gen >= 7) in mi_set_context()
503 if (INTEL_INFO(ring->dev)->gen >= 7) { in mi_set_context()
529 if (INTEL_INFO(ring->dev)->gen >= 7) { in mi_set_context()
Di915_gem_stolen.c63 if (INTEL_INFO(dev)->gen >= 3) { in i915_stolen_to_physical()
78 if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { in i915_stolen_to_physical()
185 if (ret && INTEL_INFO(dev)->gen <= 4) { in find_compression_threshold()
300 if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) { in i915_gem_init_stolen()
316 if (INTEL_INFO(dev)->gen >= 8) { in i915_gem_init_stolen()
Di915_dma.c115 if (INTEL_INFO(dev)->gen >= 4) in i915_write_hws_pga()
409 if (INTEL_INFO(dev)->gen >= 4) { in i915_emit_box()
522 if (INTEL_INFO(dev)->gen >= 4) { in i915_dispatch_batchbuffer()
989 value = INTEL_INFO(dev)->gen >= 4; in i915_getparam()
1150 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
1155 if (INTEL_INFO(dev)->gen >= 4) in intel_alloc_mchbar_resource()
1182 if (INTEL_INFO(dev)->gen >= 4) in intel_alloc_mchbar_resource()
1196 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_setup_mchbar()
1236 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_teardown_mchbar()
1365 if (INTEL_INFO(dev)->num_pipes == 0) in i915_load_modeset_init()
[all …]
Dintel_pm.c562 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { in intel_update_fbc()
565 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in intel_update_fbc()
578 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && in intel_update_fbc()
594 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && in intel_update_fbc()
2024 if (INTEL_INFO(dev)->gen >= 8) in ilk_display_fifo_size()
2026 else if (INTEL_INFO(dev)->gen >= 7) in ilk_display_fifo_size()
2035 if (INTEL_INFO(dev)->gen >= 8) in ilk_plane_wm_reg_max()
2038 else if (INTEL_INFO(dev)->gen >= 7) in ilk_plane_wm_reg_max()
2052 if (INTEL_INFO(dev)->gen >= 7) in ilk_cursor_wm_reg_max()
2060 if (INTEL_INFO(dev)->gen >= 8) in ilk_fbc_wm_reg_max()
[all …]
Dintel_display.c917 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in intel_wait_for_vblank()
988 if (INTEL_INFO(dev)->gen >= 4) { in intel_wait_for_pipe_off()
1165 if (INTEL_INFO(dev_priv->dev)->gen == 5) in assert_fdi_tx_pll_enabled()
1307 if (INTEL_INFO(dev)->gen >= 4) { in assert_planes_disabled()
1343 } else if (INTEL_INFO(dev)->gen >= 7) { in assert_sprites_disabled()
1349 } else if (INTEL_INFO(dev)->gen >= 5) { in assert_sprites_disabled()
1634 BUG_ON(INTEL_INFO(dev)->gen >= 5); in i9xx_enable_pll()
1659 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_enable_pll()
1866 BUG_ON(INTEL_INFO(dev)->gen < 5); in intel_disable_shared_dpll()
2143 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); in intel_flush_primary_plane()
[all …]
Di915_irq.c705 if (INTEL_INFO(dev)->gen >= 4) in i915_enable_asle_pipestat()
951 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()
1013 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()
1048 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { in i915_get_vblank_timestamp()
1405 if (INTEL_INFO(dev_priv->dev)->gen >= 8) in gen6_pm_rps_work()
1822 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), in intel_hpd_irq_handler()
1965 if (INTEL_INFO(dev)->gen >= 3) in i9xx_pipe_crc_irq_handler()
1970 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in i9xx_pipe_crc_irq_handler()
2493 if (INTEL_INFO(dev)->gen >= 6) in ironlake_irq_handler()
2503 if (INTEL_INFO(dev)->gen >= 7) in ironlake_irq_handler()
[all …]
Di915_gem_execbuffer.c271 if (INTEL_INFO(dev)->gen >= 8) { in relocate_entry_cpu()
315 if (INTEL_INFO(dev)->gen >= 8) { in relocate_entry_gtt()
401 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { in i915_gem_execbuffer_relocate_entry()
621 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; in i915_gem_execbuffer_reserve()
1048 if (INTEL_INFO(dev)->gen >= 5) { in i915_gem_ringbuffer_submission()
1106 if (INTEL_INFO(dev)->gen < 4) { in i915_gem_ringbuffer_submission()
1112 if (INTEL_INFO(dev)->gen > 5 && in i915_gem_ringbuffer_submission()
1120 if (INTEL_INFO(dev)->gen >= 6) in i915_gem_ringbuffer_submission()
1477 if (INTEL_INFO(dev)->gen < 4) in i915_gem_execbuffer()
Di915_debugfs.c84 const struct intel_device_info *info = INTEL_INFO(dev); in i915_capabilities()
568 if (INTEL_INFO(dev)->gen >= 4) in i915_gem_pageflip_info()
707 } else if (INTEL_INFO(dev)->gen >= 8) { in i915_interrupt_info()
828 if (INTEL_INFO(dev)->gen >= 6) { in i915_interrupt_info()
1399 else if (INTEL_INFO(dev)->gen >= 6) in i915_drpc_info()
1472 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) in i915_fbc_fc_get()
1488 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) in i915_fbc_fc_set()
1524 if (INTEL_INFO(dev)->gen >= 8) { in i915_ips_status()
1981 } else if (INTEL_INFO(dev)->gen >= 6) { in i915_swizzle_info()
2057 if (INTEL_INFO(dev)->gen == 6) in gen6_ppgtt_info()
[all …]
Di915_gem_gtt.c49 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { in sanitize_enable_ppgtt()
1093 if (INTEL_INFO(dev)->gen < 8) in __hw_ppgtt_init()
1136 else if (INTEL_INFO(dev)->gen >= 8) in i915_ppgtt_init_hw()
1253 if (INTEL_INFO(dev)->gen < 6) in i915_check_and_clear_faults()
1278 if (INTEL_INFO(dev_priv->dev)->gen < 6) { in i915_ggtt_flush()
1293 if (INTEL_INFO(dev)->gen < 6) in i915_gem_suspend_gtt_mappings()
1336 if (INTEL_INFO(dev)->gen >= 8) { in i915_gem_restore_gtt_mappings()
2084 if (INTEL_INFO(dev)->gen <= 5) { in i915_gem_gtt_init()
2087 } else if (INTEL_INFO(dev)->gen < 8) { in i915_gem_gtt_init()
2096 else if (INTEL_INFO(dev)->gen >= 7) in i915_gem_gtt_init()
[all …]
Dintel_lvds.c121 if (INTEL_INFO(dev)->gen < 4) { in intel_lvds_get_config()
190 if (INTEL_INFO(dev)->gen == 4) { in intel_pre_enable_lvds()
292 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { in intel_lvds_compute_config()
887 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) in intel_lvds_supported()
Dintel_fbdev.c455 num_connectors_enabled < INTEL_INFO(dev)->num_pipes) { in intel_fb_initial_config()
647 if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0)) in intel_fbdev_init()
660 INTEL_INFO(dev)->num_pipes, 4); in intel_fbdev_init()
Dintel_crt.c163 if (INTEL_INFO(dev)->gen >= 5) in intel_crt_set_dpms()
239 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) in intel_crt_dpms()
775 if (INTEL_INFO(dev)->gen >= 5) { in intel_crt_reset()
Di915_gem_render_state.c50 so->gen = INTEL_INFO(dev)->gen; in render_state_init()
Dintel_panel.c330 if (INTEL_INFO(dev)->gen >= 4) in intel_gmch_panel_fitting()
344 if (INTEL_INFO(dev)->gen >= 4) in intel_gmch_panel_fitting()
360 if (INTEL_INFO(dev)->gen >= 4) in intel_gmch_panel_fitting()
371 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) in intel_gmch_panel_fitting()
507 if (INTEL_INFO(dev)->gen < 4) in i9xx_get_backlight()
Di915_gem.c177 if (INTEL_INFO(dev)->gen >= 5) in i915_gem_init_ioctl()
1176 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { in __wait_seqno()
1680 if (INTEL_INFO(dev)->gen >= 4 || in i915_gem_get_gtt_size()
1685 if (INTEL_INFO(dev)->gen == 3) in i915_gem_get_gtt_size()
1711 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || in i915_gem_get_gtt_alignment()
3027 if (INTEL_INFO(dev)->gen >= 6) { in i965_write_fence_reg()
3175 switch (INTEL_INFO(dev)->gen) { in i915_gem_write_fence()
3740 if (INTEL_INFO(dev)->gen < 6) { in i915_gem_object_set_cache_level()
4659 if (INTEL_INFO(dev)->gen < 5 || in i915_gem_init_swizzling()
4790 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) in i915_gem_init_hw()
[all …]
Dintel_uncore.c123 if (INTEL_INFO(dev_priv->dev)->gen < 8) in __gen7_gt_force_wake_mt_get()
882 switch (INTEL_INFO(dev)->gen) { in intel_uncore_init()
984 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) in i915_reg_read_ioctl()
1170 if (INTEL_INFO(dev)->gen >= 6) in intel_gpu_reset()
Di915_drv.c414 if (INTEL_INFO(dev)->num_pipes == 0) { in intel_detect_pch()
478 if (INTEL_INFO(dev)->gen < 6) in i915_semaphore_is_enabled()
494 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) in i915_semaphore_is_enabled()
873 if (INTEL_INFO(dev)->gen > 5) in i915_reset()
Di915_sysfs.c598 if (INTEL_INFO(dev)->gen >= 6) { in i915_setup_sysfs()
621 else if (INTEL_INFO(dev)->gen >= 6) in i915_setup_sysfs()
Dintel_sdvo.c1258 if (INTEL_INFO(dev)->gen >= 4) { in intel_sdvo_pre_enable()
1264 if (INTEL_INFO(dev)->gen < 5) in intel_sdvo_pre_enable()
1287 if (INTEL_INFO(dev)->gen >= 4) { in intel_sdvo_pre_enable()
1297 INTEL_INFO(dev)->gen < 5) in intel_sdvo_pre_enable()
2463 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { in intel_sdvo_add_hdmi_properties()

12