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Searched refs:write_reg (Results 1 – 25 of 95) sorted by relevance

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/drivers/media/pci/ivtv/
Divtv-yuv.c179 write_reg(read_dec(i), 0x02804); in ivtv_yuv_filter()
180 write_reg(read_dec(i), 0x0281c); in ivtv_yuv_filter()
182 write_reg(read_dec(i), 0x02808); in ivtv_yuv_filter()
183 write_reg(read_dec(i), 0x02820); in ivtv_yuv_filter()
185 write_reg(read_dec(i), 0x0280c); in ivtv_yuv_filter()
186 write_reg(read_dec(i), 0x02824); in ivtv_yuv_filter()
188 write_reg(read_dec(i), 0x02810); in ivtv_yuv_filter()
189 write_reg(read_dec(i), 0x02828); in ivtv_yuv_filter()
191 write_reg(read_dec(i), 0x02814); in ivtv_yuv_filter()
192 write_reg(read_dec(i), 0x0282c); in ivtv_yuv_filter()
[all …]
Divtv-gpio.c116 write_reg(curdir, IVTV_REG_GPIO_DIR); in ivtv_reset_ir_gpio()
118 write_reg(curout, IVTV_REG_GPIO_OUT); in ivtv_reset_ir_gpio()
122 write_reg(curout, IVTV_REG_GPIO_OUT); in ivtv_reset_ir_gpio()
124 write_reg(curdir, IVTV_REG_GPIO_DIR); in ivtv_reset_ir_gpio()
139 write_reg(curout, IVTV_REG_GPIO_OUT); in ivtv_reset_tuner_gpio()
143 write_reg(curout, IVTV_REG_GPIO_OUT); in ivtv_reset_tuner_gpio()
177 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_clock_freq()
218 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_tuner()
230 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_radio()
256 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_audio_routing()
[all …]
Divtv-firmware.c100 write_reg(IVTV_CMD_VDM_STOP, IVTV_REG_VDM); in ivtv_halt_firmware()
103 write_reg(IVTV_CMD_AO_STOP, IVTV_REG_AO); in ivtv_halt_firmware()
106 write_reg(IVTV_CMD_APU_PING, IVTV_REG_APU); in ivtv_halt_firmware()
110 write_reg(IVTV_CMD_VPU_STOP16, IVTV_REG_VPU); in ivtv_halt_firmware()
112 write_reg(IVTV_CMD_VPU_STOP15, IVTV_REG_VPU); in ivtv_halt_firmware()
115 write_reg(IVTV_CMD_HW_BLOCKS_RST, IVTV_REG_HW_BLOCKS); in ivtv_halt_firmware()
118 write_reg(IVTV_CMD_SPU_STOP, IVTV_REG_SPU); in ivtv_halt_firmware()
123 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INIT, IVTV_REG_ENC_SDRAM_PRECHARGE); in ivtv_halt_firmware()
126 write_reg(IVTV_CMD_SDRAM_REFRESH_INIT, IVTV_REG_ENC_SDRAM_REFRESH); in ivtv_halt_firmware()
130 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INIT, IVTV_REG_DEC_SDRAM_PRECHARGE); in ivtv_halt_firmware()
[all …]
/drivers/media/radio/
Dradio-tea5777.c198 tea->write_reg &= ~TEA5777_W_AM_FM_MASK; in radio_tea5777_set_freq()
200 tea->write_reg &= ~TEA5777_W_FM_PLL_MASK; in radio_tea5777_set_freq()
201 tea->write_reg |= (u64)freq << TEA5777_W_FM_PLL_SHIFT; in radio_tea5777_set_freq()
202 tea->write_reg &= ~TEA5777_W_FM_FREF_MASK; in radio_tea5777_set_freq()
203 tea->write_reg |= TEA5777_W_FM_FREF_VALUE << in radio_tea5777_set_freq()
205 tea->write_reg &= ~TEA5777_W_FM_FORCEMONO_MASK; in radio_tea5777_set_freq()
207 tea->write_reg |= 1LL << TEA5777_W_FM_FORCEMONO_SHIFT; in radio_tea5777_set_freq()
210 tea->write_reg &= ~TEA5777_W_AM_FM_MASK; in radio_tea5777_set_freq()
211 tea->write_reg |= (1LL << TEA5777_W_AM_FM_SHIFT); in radio_tea5777_set_freq()
213 tea->write_reg &= ~TEA5777_W_AM_PLL_MASK; in radio_tea5777_set_freq()
[all …]
/drivers/staging/media/cxd2099/
Dcxd2099.c230 static int write_reg(struct cxd *ci, u8 reg, u8 val) in write_reg() function
305 status = write_reg(ci, 0x00, 0x00); in init()
308 status = write_reg(ci, 0x01, 0x00); in init()
311 status = write_reg(ci, 0x02, 0x10); in init()
314 status = write_reg(ci, 0x03, 0x00); in init()
317 status = write_reg(ci, 0x05, 0xFF); in init()
320 status = write_reg(ci, 0x06, 0x1F); in init()
323 status = write_reg(ci, 0x07, 0x1F); in init()
326 status = write_reg(ci, 0x08, 0x28); in init()
329 status = write_reg(ci, 0x14, 0x20); in init()
[all …]
/drivers/net/ethernet/intel/igb/
De1000_phy.c88 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_get_phy_id()
117 if (!(hw->phy.ops.write_reg)) in igb_phy_reset_dsp()
120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); in igb_phy_reset_dsp()
124 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); in igb_phy_reset_dsp()
510 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); in igb_copper_link_setup_82580()
535 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); in igb_copper_link_setup_82580()
601 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in igb_copper_link_setup_m88()
628 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, in igb_copper_link_setup_m88()
708 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in igb_copper_link_setup_m88_gen2()
723 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in igb_copper_link_setup_m88_gen2()
[all …]
/drivers/net/can/sja1000/
Dsja1000.c94 priv->write_reg(priv, SJA1000_CMR, val); in sja1000_write_cmdreg()
122 priv->write_reg(priv, SJA1000_IER, IRQ_OFF); in set_reset_mode()
132 priv->write_reg(priv, SJA1000_MOD, MOD_RM); in set_reset_mode()
153 priv->write_reg(priv, SJA1000_IER, IRQ_ALL); in set_normal_mode()
155 priv->write_reg(priv, SJA1000_IER, in set_normal_mode()
165 priv->write_reg(priv, SJA1000_MOD, mod_reg_val); in set_normal_mode()
188 priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN); in chipset_init()
191 priv->write_reg(priv, SJA1000_ACCC0, 0x00); in chipset_init()
192 priv->write_reg(priv, SJA1000_ACCC1, 0x00); in chipset_init()
193 priv->write_reg(priv, SJA1000_ACCC2, 0x00); in chipset_init()
[all …]
Dsja1000_platform.c85 priv->write_reg = sp_write_reg32; in sp_populate()
89 priv->write_reg = sp_write_reg16; in sp_populate()
94 priv->write_reg = sp_write_reg8; in sp_populate()
111 priv->write_reg = sp_write_reg32; in sp_populate_of()
115 priv->write_reg = sp_write_reg16; in sp_populate_of()
120 priv->write_reg = sp_write_reg8; in sp_populate_of()
/drivers/net/can/
Dxilinx_can.c139 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, member
229 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in set_reset_mode()
280 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); in xcan_set_bittiming()
281 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); in xcan_set_bittiming()
317 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL); in xcan_chip_start()
328 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); in xcan_chip_start()
329 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); in xcan_chip_start()
444 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id); in xcan_start_xmit()
446 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc); in xcan_start_xmit()
448 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]); in xcan_start_xmit()
[all …]
/drivers/tty/
Dsynclinkmp.c622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
1543 write_reg(info, CTL, RegValue); in set_break()
2086 write_reg(info, IER2, 0); in isr_timer()
2098 write_reg(info, (unsigned char)(timer + TMCS), 0); in isr_timer()
2116 write_reg(info, SR1, status); in isr_rxint()
2119 write_reg(info, SR2, status2); in isr_rxint()
2234 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ in isr_txeom()
2235 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ in isr_txeom()
2236 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in isr_txeom()
2239 write_reg(info, CMD, TXRESET); in isr_txeom()
[all …]
/drivers/macintosh/
Dtherm_windtunnel.c120 write_reg( struct i2c_client *cl, int reg, int data, int len ) in write_reg() function
158 write_reg( x.fan, 0x25, val, 1 ); in tune_fan()
159 write_reg( x.fan, 0x20, 0, 1 ); in tune_fan()
224 if( write_reg( x.thermostat, 1, val, 1 ) ) in setup_hardware()
228 write_reg( x.fan, 0x01, 0x01, 1 ); in setup_hardware()
230 write_reg( x.fan, 0x23, 0x91, 1 ); in setup_hardware()
232 write_reg( x.fan, 0x00, 0x95, 1 ); in setup_hardware()
242 write_reg( x.thermostat, 2, x.overheat_hyst, 2 ); in setup_hardware()
243 write_reg( x.thermostat, 3, x.overheat_temp, 2 ); in setup_hardware()
268 write_reg( x.fan, 0x01, x.r1, 1 ); in restore_regs()
[all …]
/drivers/media/i2c/
Dtw2804.c118 static int write_reg(struct i2c_client *client, u8 reg, u8 value, u8 channel) in write_reg() function
218 return write_reg(client, addr, reg, state->channel); in tw2804_s_ctrl()
226 return write_reg(client, addr, reg, state->channel); in tw2804_s_ctrl()
229 return write_reg(client, TW2804_REG_GAIN, ctrl->val, 0); in tw2804_s_ctrl()
232 return write_reg(client, TW2804_REG_CHROMA_GAIN, ctrl->val, 0); in tw2804_s_ctrl()
235 return write_reg(client, TW2804_REG_BLUE_BALANCE, ctrl->val, 0); in tw2804_s_ctrl()
238 return write_reg(client, TW2804_REG_RED_BALANCE, ctrl->val, 0); in tw2804_s_ctrl()
241 return write_reg(client, TW2804_REG_BRIGHTNESS, in tw2804_s_ctrl()
245 return write_reg(client, TW2804_REG_CONTRAST, in tw2804_s_ctrl()
249 return write_reg(client, TW2804_REG_SATURATION, in tw2804_s_ctrl()
[all …]
Duda1342.c26 static int write_reg(struct i2c_client *client, int reg, int value) in write_reg() function
40 write_reg(client, 0x00, 0x1241); /* select input 1 */ in uda1342_s_routing()
43 write_reg(client, 0x00, 0x1441); /* select input 2 */ in uda1342_s_routing()
78 write_reg(client, 0x00, 0x8000); /* reset registers */ in uda1342_probe()
79 write_reg(client, 0x00, 0x1241); /* select input 1 */ in uda1342_probe()
Dtw9903.c102 static int write_reg(struct v4l2_subdev *sd, u8 reg, u8 value) in write_reg() function
114 if (write_reg(sd, regs[i], regs[i + 1]) < 0) in write_regs()
122 write_reg(sd, 0x02, 0x40 | (input << 1)); in tw9903_s_video_routing()
158 write_reg(sd, 0x10, ctrl->val); in tw9903_s_ctrl()
161 write_reg(sd, 0x11, ctrl->val); in tw9903_s_ctrl()
164 write_reg(sd, 0x15, ctrl->val); in tw9903_s_ctrl()
Dtw9906.c73 static int write_reg(struct v4l2_subdev *sd, u8 reg, u8 value) in write_reg() function
85 if (write_reg(sd, regs[i], regs[i + 1]) < 0) in write_regs()
93 write_reg(sd, 0x02, 0x40 | (input << 1)); in tw9906_s_video_routing()
128 write_reg(sd, 0x10, ctrl->val); in tw9906_s_ctrl()
131 write_reg(sd, 0x11, ctrl->val); in tw9906_s_ctrl()
134 write_reg(sd, 0x15, ctrl->val); in tw9906_s_ctrl()
/drivers/rtc/
Drtc-r9701.c43 static int write_reg(struct device *dev, int address, unsigned char data) in write_reg() function
106 ret = write_reg(dev, RHRCNT, bin2bcd(dt->tm_hour)); in r9701_set_datetime()
107 ret = ret ? ret : write_reg(dev, RMINCNT, bin2bcd(dt->tm_min)); in r9701_set_datetime()
108 ret = ret ? ret : write_reg(dev, RSECCNT, bin2bcd(dt->tm_sec)); in r9701_set_datetime()
109 ret = ret ? ret : write_reg(dev, RDAYCNT, bin2bcd(dt->tm_mday)); in r9701_set_datetime()
110 ret = ret ? ret : write_reg(dev, RMONCNT, bin2bcd(dt->tm_mon + 1)); in r9701_set_datetime()
111 ret = ret ? ret : write_reg(dev, RYRCNT, bin2bcd(dt->tm_year - 100)); in r9701_set_datetime()
112 ret = ret ? ret : write_reg(dev, RWKCNT, 1 << dt->tm_wday); in r9701_set_datetime()
/drivers/video/fbdev/mbx/
Dmbxfb.c38 #define write_reg(val, reg) do { writel((val), (reg)); } while(0) macro
448 write_reg(vsctrl, VSCTRL); in mbxfb_setupOverlay()
449 write_reg(vscadr, VSCADR); in mbxfb_setupOverlay()
450 write_reg(vubase, VUBASE); in mbxfb_setupOverlay()
451 write_reg(vvbase, VVBASE); in mbxfb_setupOverlay()
452 write_reg(vsadr, VSADR); in mbxfb_setupOverlay()
455 write_reg(sssize, SSSIZE); in mbxfb_setupOverlay()
456 write_reg(spoctrl, SPOCTRL); in mbxfb_setupOverlay()
457 write_reg(shctrl, SHCTRL); in mbxfb_setupOverlay()
465 write_reg(vovrclk, VOVRCLK); in mbxfb_setupOverlay()
[all …]
/drivers/gpio/
Dgpio-generic.c158 bgc->write_reg(bgc->reg_dat, bgc->data); in bgpio_set()
170 bgc->write_reg(bgc->reg_set, mask); in bgpio_set_with_clear()
172 bgc->write_reg(bgc->reg_clr, mask); in bgpio_set_with_clear()
188 bgc->write_reg(bgc->reg_set, bgc->data); in bgpio_set_set()
214 bgc->write_reg(bgc->reg_dir, bgc->dir); in bgpio_dir_in()
231 bgc->write_reg(bgc->reg_dir, bgc->dir); in bgpio_dir_out()
246 bgc->write_reg(bgc->reg_dir, bgc->dir); in bgpio_dir_in_inv()
263 bgc->write_reg(bgc->reg_dir, bgc->dir); in bgpio_dir_out_inv()
279 bgc->write_reg = bgpio_write8; in bgpio_setup_accessors()
284 bgc->write_reg = bgpio_write16be; in bgpio_setup_accessors()
[all …]
/drivers/ide/
Dopti621.c38 static void write_reg(u8 value, int reg) in write_reg() function
113 write_reg(drive->dn & 1, MISC_REG); in opti621_set_pio_mode()
115 write_reg(tim, READ_REG); in opti621_set_pio_mode()
117 write_reg(tim, WRITE_REG); in opti621_set_pio_mode()
121 write_reg(0x85, CNTRL_REG); in opti621_set_pio_mode()
125 write_reg(misc, MISC_REG); in opti621_set_pio_mode()
/drivers/net/ethernet/realtek/
Datp.c273 write_reg(ioaddr, MODSEL, 0x00); in atp_probe1()
321 write_reg(ioaddr, CMR2, CMR2_NULL); in atp_probe1()
374 write_reg(ioaddr, CMR2, CMR2_EEPROM); /* Point to the EEPROM control registers. */ in get_node_ID()
385 write_reg(ioaddr, CMR2, CMR2_NULL); in get_node_ID()
475 write_reg(ioaddr, CMR2, CMR2_IRQOUT); in hardware_init()
482 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); in hardware_init()
493 write_reg(ioaddr, TxCNT1, length >> 8); in trigger_send()
494 write_reg(ioaddr, CMR1, CMR1_Xmit); in trigger_send()
568 write_reg(ioaddr, IMR, 0); in atp_send_packet()
583 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); in atp_send_packet()
[all …]
/drivers/net/can/c_can/
Dc_can.c247 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); in c_can_irq_control()
287 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); in c_can_inval_tx_object()
295 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); in c_can_inval_msg_object()
296 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); in c_can_inval_msg_object()
332 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); in c_can_setup_tx_object()
346 priv->write_reg(priv, in c_can_setup_tx_object()
372 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); in c_can_handle_lost_msg_obj()
453 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); in c_can_setup_receive_object()
534 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); in c_can_set_bittiming()
539 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); in c_can_set_bittiming()
[all …]
Dc_can_pci.c99 priv->write_reg(priv, index + 1, val >> 16); in c_can_pci_write_reg32()
100 priv->write_reg(priv, index, val); in c_can_pci_write_reg32()
192 priv->write_reg = c_can_pci_write_reg_aligned_to_32bit; in c_can_pci_probe()
196 priv->write_reg = c_can_pci_write_reg_aligned_to_16bit; in c_can_pci_probe()
200 priv->write_reg = c_can_pci_write_reg_32bit; in c_can_pci_probe()
/drivers/isdn/hardware/mISDN/
Dhfcsusb.c90 static int write_reg(struct hfcsusb *hw, __u8 reg, __u8 val) in write_reg() function
202 write_reg(hw, HFCUSB_P_DATA, hw->led_state); in handle_led()
657 write_reg(hw, HFCUSB_STATES, 2 | HFCUSB_NT_G2_G3); in ph_state_nt()
736 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 0 : 2); in hfcsusb_setup_bch()
737 write_reg(hw, HFCUSB_CON_HDLC, conhdlc); in hfcsusb_setup_bch()
738 write_reg(hw, HFCUSB_INC_RES_F, 2); in hfcsusb_setup_bch()
739 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 1 : 3); in hfcsusb_setup_bch()
740 write_reg(hw, HFCUSB_CON_HDLC, conhdlc); in hfcsusb_setup_bch()
741 write_reg(hw, HFCUSB_INC_RES_F, 2); in hfcsusb_setup_bch()
753 write_reg(hw, HFCUSB_SCTRL, sctrl); in hfcsusb_setup_bch()
[all …]
DmISDNisar.c75 isar->write_reg(isar->hw, ISAR_CTRL_H, creg); in send_mbox()
76 isar->write_reg(isar->hw, ISAR_CTRL_L, len); in send_mbox()
77 isar->write_reg(isar->hw, ISAR_WADR, 0); in send_mbox()
94 isar->write_reg(isar->hw, ISAR_HIS, his); in send_mbox()
108 isar->write_reg(isar->hw, ISAR_RADR, 0); in rcv_mbox()
123 isar->write_reg(isar->hw, ISAR_IIA, 0); in rcv_mbox()
167 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); in ISARVersion()
214 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); in load_firmware()
323 isar->write_reg(isar->hw, ISAR_IRQBIT, ISAR_IRQSTA); in load_firmware()
409 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); in load_firmware()
[all …]
/drivers/char/pcmcia/
Dsynclink_cs.c321 #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg)) macro
328 write_reg(info, (reg), \
331 write_reg(info, (reg), \
358 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
361 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
701 write_reg(info, (unsigned char) (channel + CMDR), cmd); in issue_command()
1025 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get)); in tx_ready()
1888 write_reg(info, PVR, val); in set_interface()
2930 write_reg(info, (unsigned char) (channel + BGR), in mgslpc_set_rate()
2934 write_reg(info, (unsigned char) (channel + CCR2), val); in mgslpc_set_rate()
[all …]

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