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/arch/mips/include/asm/mach-pnx8550/
Duart.h18 #define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000) argument
19 #define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004) argument
20 #define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008) argument
21 #define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C) argument
22 #define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028) argument
23 #define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0) argument
24 #define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4) argument
25 #define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8) argument
26 #define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC) argument
27 #define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4) argument
[all …]
/arch/arm/boot/compressed/
Dsdhi-shmobile.c29 static inline u16 sd_ctrl_read16(void __iomem *base, int addr) in sd_ctrl_read16() argument
31 return __raw_readw(base + addr); in sd_ctrl_read16()
34 static inline u32 sd_ctrl_read32(void __iomem *base, int addr) in sd_ctrl_read32() argument
36 return __raw_readw(base + addr) | in sd_ctrl_read32()
37 __raw_readw(base + addr + 2) << 16; in sd_ctrl_read32()
40 static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val) in sd_ctrl_write16() argument
42 __raw_writew(val, base + addr); in sd_ctrl_write16()
45 static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val) in sd_ctrl_write32() argument
47 __raw_writew(val, base + addr); in sd_ctrl_write32()
48 __raw_writew(val >> 16, base + addr + 2); in sd_ctrl_write32()
[all …]
/arch/powerpc/include/asm/
Dppc_asm.h80 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) argument
81 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) argument
82 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) argument
83 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) argument
85 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) argument
86 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) argument
87 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ argument
88 SAVE_10GPRS(22, base)
89 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ argument
90 REST_10GPRS(22, base)
[all …]
/arch/arm/common/
Dvic.c51 void __iomem *base; member
74 static void vic_init2(void __iomem *base) in vic_init2() argument
79 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); in vic_init2()
83 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init2()
89 void __iomem *base = vic->base; in resume_one_vic() local
91 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); in resume_one_vic()
94 vic_init2(base); in resume_one_vic()
96 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic()
97 writel(vic->protect, base + VIC_PROTECT); in resume_one_vic()
100 writel(vic->int_enable, base + VIC_INT_ENABLE); in resume_one_vic()
[all …]
/arch/arm/mach-ixp2000/include/mach/
Dentry-macro.S12 .macro get_irqnr_preamble, base, tmp
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
18 mov \base, #0xfe000000
19 orr \base, \base, #0x00e00000
20 orr \base, \base, #0x08
21 ldr \irqstat, [\base] @ get interrupts
27 mov \base, #31
28 subs \irqnr, \base, \irqnr
37 mov \base, #0xfe000000
38 orr \base, \base, #0x00c00000
[all …]
/arch/arm/plat-orion/
Dpcie.c55 u32 __init orion_pcie_dev_id(void __iomem *base) in orion_pcie_dev_id() argument
57 return readl(base + PCIE_DEV_ID_OFF) >> 16; in orion_pcie_dev_id()
60 u32 __init orion_pcie_rev(void __iomem *base) in orion_pcie_rev() argument
62 return readl(base + PCIE_DEV_REV_OFF) & 0xff; in orion_pcie_rev()
65 int orion_pcie_link_up(void __iomem *base) in orion_pcie_link_up() argument
67 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); in orion_pcie_link_up()
70 int __init orion_pcie_x4_mode(void __iomem *base) in orion_pcie_x4_mode() argument
72 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); in orion_pcie_x4_mode()
75 int orion_pcie_get_local_bus_nr(void __iomem *base) in orion_pcie_get_local_bus_nr() argument
77 u32 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_get_local_bus_nr()
[all …]
/arch/arm/mach-s5p64x0/
Dgpiolib.c70 void __iomem *base = ourchip->base; in s5p64x0_gpiolib_rbank_4bit2_input() local
71 void __iomem *regcon = base; in s5p64x0_gpiolib_rbank_4bit2_input()
106 void __iomem *base = ourchip->base; in s5p64x0_gpiolib_rbank_4bit2_output() local
107 void __iomem *regcon = base; in s5p64x0_gpiolib_rbank_4bit2_output()
135 dat = __raw_readl(base + GPIODAT_OFF); in s5p64x0_gpiolib_rbank_4bit2_output()
142 __raw_writel(dat, base + GPIODAT_OFF); in s5p64x0_gpiolib_rbank_4bit2_output()
152 void __iomem *reg = chip->base; in s5p64x0_gpio_setcfg_4bit_rbank()
212 .base = S5P64X0_GPA_BASE,
215 .base = S5P6440_GPA(0),
220 .base = S5P64X0_GPB_BASE,
[all …]
/arch/arm/mach-cns3xxx/include/mach/
Duncompress.h13 #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) argument
14 #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) argument
15 #define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) argument
16 #define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) argument
34 unsigned long base = get_uart_base(); in putc() local
36 while (AMBA_UART_FR(base) & (1 << 5)) in putc()
39 AMBA_UART_DR(base) = c; in putc()
44 unsigned long base = get_uart_base(); in flush() local
46 while (AMBA_UART_FR(base) & (1 << 3)) in flush()
/arch/m68k/amiga/
Dcia.c50 unsigned char cia_set_irq(struct ciabase *base, unsigned char mask) in cia_set_irq() argument
54 old = (base->icr_data |= base->cia->icr); in cia_set_irq()
56 base->icr_data |= mask; in cia_set_irq()
58 base->icr_data &= ~mask; in cia_set_irq()
59 if (base->icr_data & base->icr_mask) in cia_set_irq()
60 amiga_custom.intreq = IF_SETCLR | base->int_mask; in cia_set_irq()
61 return old & base->icr_mask; in cia_set_irq()
68 unsigned char cia_able_irq(struct ciabase *base, unsigned char mask) in cia_able_irq() argument
72 old = base->icr_mask; in cia_able_irq()
73 base->icr_data |= base->cia->icr; in cia_able_irq()
[all …]
/arch/alpha/kernel/
Dpc873xx.c12 static unsigned int base, model; variable
17 return base; in pc873xx_get_base()
25 static unsigned char __init pc873xx_read(unsigned int base, int reg) in pc873xx_read() argument
27 outb(reg, base); in pc873xx_read()
28 return inb(base + 1); in pc873xx_read()
31 static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) in pc873xx_write() argument
36 outb(reg, base); in pc873xx_write()
37 outb(data, base + 1); in pc873xx_write()
38 outb(data, base + 1); /* Must be written twice */ in pc873xx_write()
46 while ((base = pc873xx_probelist[index++])) { in pc873xx_probe()
[all …]
/arch/arm/mach-vexpress/include/mach/
Duncompress.h20 #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) argument
21 #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) argument
22 #define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) argument
23 #define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) argument
52 unsigned long base = get_uart_base(); in putc() local
54 while (AMBA_UART_FR(base) & (1 << 5)) in putc()
57 AMBA_UART_DR(base) = c; in putc()
62 unsigned long base = get_uart_base(); in flush() local
64 while (AMBA_UART_FR(base) & (1 << 3)) in flush()
/arch/arm/include/asm/
Dcti.h53 void __iomem *base; member
70 void __iomem *base, int irq, int trig_out) in cti_init() argument
72 cti->base = base; in cti_init()
90 void __iomem *base = cti->base; in cti_map_trigger() local
93 val = __raw_readl(base + CTIINEN + trig_in * 4); in cti_map_trigger()
95 __raw_writel(val, base + CTIINEN + trig_in * 4); in cti_map_trigger()
97 val = __raw_readl(base + CTIOUTEN + trig_out * 4); in cti_map_trigger()
99 __raw_writel(val, base + CTIOUTEN + trig_out * 4); in cti_map_trigger()
110 __raw_writel(0x1, cti->base + CTICONTROL); in cti_enable()
121 __raw_writel(0, cti->base + CTICONTROL); in cti_disable()
[all …]
Dvfpmacros.h20 .macro VFPFLDMIA, base, tmp in toolkits()
22 LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} in toolkits()
24 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
31 ldcnel p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
32 addeq \base, \base, #32*4 @ step over unused register space
37 ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
38 addne \base, \base, #32*4 @ step over unused register space
44 .macro VFPFSTMIA, base, tmp
46 STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
48 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
[all …]
/arch/arm/mach-realview/include/mach/
Duncompress.h29 #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) argument
30 #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) argument
31 #define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) argument
32 #define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) argument
58 unsigned long base = get_uart_base(); in putc() local
60 while (AMBA_UART_FR(base) & (1 << 5)) in putc()
63 AMBA_UART_DR(base) = c; in putc()
68 unsigned long base = get_uart_base(); in flush() local
70 while (AMBA_UART_FR(base) & (1 << 3)) in flush()
/arch/sparc/kernel/
Dkstack.h12 unsigned long base = (unsigned long) tp; in kstack_valid() local
18 if (sp >= (base + sizeof(struct thread_info)) && in kstack_valid()
19 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) in kstack_valid()
23 base = (unsigned long) hardirq_stack[tp->cpu]; in kstack_valid()
24 if (sp >= base && in kstack_valid()
25 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) in kstack_valid()
27 base = (unsigned long) softirq_stack[tp->cpu]; in kstack_valid()
28 if (sp >= base && in kstack_valid()
29 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) in kstack_valid()
38 unsigned long base = (unsigned long) tp; in kstack_is_trap_frame() local
[all …]
Dbtext.c22 static void draw_byte_32(unsigned char *bits, unsigned int *base, int rb);
23 static void draw_byte_16(unsigned char *bits, unsigned int *base, int rb);
24 static void draw_byte_8(unsigned char *bits, unsigned int *base, int rb);
89 unsigned char *base = dispDeviceBase; in calc_base() local
91 base += (x + dispDeviceRect[0]) * (dispDeviceDepth >> 3); in calc_base()
92 base += (y + dispDeviceRect[1]) * dispDeviceRowBytes; in calc_base()
93 return base; in calc_base()
98 unsigned int *base = (unsigned int *)calc_base(0, 0); in btext_clearscreen() local
105 unsigned int *ptr = base; in btext_clearscreen()
108 base += (dispDeviceRowBytes >> 2); in btext_clearscreen()
[all …]
/arch/arm/mach-tegra/
Dusb_phy.c247 void __iomem *base = phy->pad_regs; in utmip_pad_power_on() local
254 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
256 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
267 void __iomem *base = phy->pad_regs; in utmip_pad_power_off() local
279 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
281 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
306 void __iomem *base = phy->regs; in utmi_phy_clk_disable() local
309 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
311 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
315 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
[all …]
/arch/mips/alchemy/common/
Dvss.c24 void __iomem *base = (void __iomem *)VSS_ADDR(block); in __enable_block() local
26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
29 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
33 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
35 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
37 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
39 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
42 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
[all …]
Dirq.c291 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_unmask() local
293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
301 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_unmask() local
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
311 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_mask() local
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
321 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_mask() local
[all …]
/arch/s390/lib/
Ddiv64.c19 static uint32_t __div64_31(uint64_t *n, uint32_t base) in __div64_31() argument
27 if (base == 1) in __div64_31()
40 : "+d" (reg2), "+d" (reg3) : "d" (base) : "cc" ); in __div64_31()
67 : "d" (base), "2" (1UL) : "cc" ); in __div64_31()
76 uint32_t __div64_32(uint64_t *n, uint32_t base) in __div64_32() argument
87 r = __div64_31(n, ((signed) base < 0) ? (base/2) : base); in __div64_32()
88 if ((signed) base < 0) { in __div64_32()
99 r += base/2; in __div64_32()
107 if (base & 1) { in __div64_32()
117 rx += base; in __div64_32()
[all …]
/arch/mips/ath79/
Dgpio.c31 void __iomem *base = ath79_gpio_base; in __ath79_gpio_set_value() local
34 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET); in __ath79_gpio_set_value()
36 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR); in __ath79_gpio_set_value()
58 void __iomem *base = ath79_gpio_base; in ath79_gpio_direction_input() local
63 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), in ath79_gpio_direction_input()
64 base + AR71XX_GPIO_REG_OE); in ath79_gpio_direction_input()
74 void __iomem *base = ath79_gpio_base; in ath79_gpio_direction_output() local
80 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); in ath79_gpio_direction_output()
82 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); in ath79_gpio_direction_output()
84 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), in ath79_gpio_direction_output()
[all …]
/arch/x86/mm/
Damdtopology.c99 u64 base, limit; in amd_numa_init() local
101 base = read_pci_config(0, nb, 1, 0x40 + i*8); in amd_numa_init()
105 if ((base & 3) == 0) { in amd_numa_init()
112 base, limit); in amd_numa_init()
118 i, base); in amd_numa_init()
121 if ((base >> 8) & 3 || (limit >> 8) & 3) { in amd_numa_init()
123 nodeid, (base >> 8) & 3, (limit >> 8) & 3); in amd_numa_init()
139 if (limit <= base) in amd_numa_init()
142 base >>= 16; in amd_numa_init()
143 base <<= 24; in amd_numa_init()
[all …]
/arch/arm/plat-samsung/
Dpm-gpio.c33 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save()
34 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save()
39 void __iomem *base = chip->base; in samsung_gpio_pm_1bit_resume() local
40 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
41 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
52 __raw_writel(gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
56 __raw_writel(gps_gpdat, base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
57 __raw_writel(gps_gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
70 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_2bit_save()
71 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_2bit_save()
[all …]
/arch/mips/include/asm/netlogic/
Dhaldefs.h75 nlm_read_reg(uint64_t base, uint32_t reg) in nlm_read_reg() argument
77 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; in nlm_read_reg()
83 nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) in nlm_write_reg() argument
85 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; in nlm_write_reg()
91 nlm_read_reg64(uint64_t base, uint32_t reg) in nlm_read_reg64() argument
93 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); in nlm_read_reg64()
100 nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) in nlm_write_reg64() argument
102 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); in nlm_write_reg64()
113 nlm_read_reg_xkphys(uint64_t base, uint32_t reg) in nlm_read_reg_xkphys() argument
115 return nlm_read_reg(base, reg); in nlm_read_reg_xkphys()
[all …]
/arch/arm/plat-mxc/
Dcpu.c23 void __init imx_set_aips(void __iomem *base) in imx_set_aips() argument
30 __raw_writel(0x77777777, base + 0x0); in imx_set_aips()
31 __raw_writel(0x77777777, base + 0x4); in imx_set_aips()
38 __raw_writel(0x0, base + 0x40); in imx_set_aips()
39 __raw_writel(0x0, base + 0x44); in imx_set_aips()
40 __raw_writel(0x0, base + 0x48); in imx_set_aips()
41 __raw_writel(0x0, base + 0x4C); in imx_set_aips()
42 reg = __raw_readl(base + 0x50) & 0x00FFFFFF; in imx_set_aips()
43 __raw_writel(reg, base + 0x50); in imx_set_aips()

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