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Searched refs:dd (Results 1 – 25 of 132) sorted by relevance

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/drivers/crypto/
Domap-des.c50 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
52 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ argument
55 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) argument
57 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) argument
64 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) argument
66 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs) argument
68 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs) argument
72 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) argument
73 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) argument
89 struct omap_des_dev *dd; member
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Domap-aes.c50 #define omap_aes_read(dd, offset) \ argument
53 _read_ret = __raw_readl(dd->io_base + offset); \
59 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) in omap_aes_read() argument
61 return __raw_readl(dd->io_base + offset); in omap_aes_read()
66 #define omap_aes_write(dd, offset, value) \ argument
70 __raw_writel(value, dd->io_base + offset); \
73 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, in omap_aes_write() argument
76 __raw_writel(value, dd->io_base + offset); in omap_aes_write()
80 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, in omap_aes_write_mask() argument
85 val = omap_aes_read(dd, offset); in omap_aes_write_mask()
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Datmel-tdes.c75 struct atmel_tdes_dev *dd; member
181 static inline u32 atmel_tdes_read(struct atmel_tdes_dev *dd, u32 offset) in atmel_tdes_read() argument
183 return readl_relaxed(dd->io_base + offset); in atmel_tdes_read()
186 static inline void atmel_tdes_write(struct atmel_tdes_dev *dd, in atmel_tdes_write() argument
189 writel_relaxed(value, dd->io_base + offset); in atmel_tdes_write()
192 static void atmel_tdes_write_n(struct atmel_tdes_dev *dd, u32 offset, in atmel_tdes_write_n() argument
196 atmel_tdes_write(dd, offset, *value); in atmel_tdes_write_n()
205 if (!ctx->dd) { in atmel_tdes_find_dev()
210 ctx->dd = tdes_dd; in atmel_tdes_find_dev()
212 tdes_dd = ctx->dd; in atmel_tdes_find_dev()
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Datmel-aes.c107 struct atmel_aes_dev *dd; member
345 static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset) in atmel_aes_read() argument
347 u32 value = readl_relaxed(dd->io_base + offset); in atmel_aes_read()
350 if (dd->flags & AES_FLAGS_DUMP_REG) { in atmel_aes_read()
353 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value, in atmel_aes_read()
361 static inline void atmel_aes_write(struct atmel_aes_dev *dd, in atmel_aes_write() argument
365 if (dd->flags & AES_FLAGS_DUMP_REG) { in atmel_aes_write()
368 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value, in atmel_aes_write()
373 writel_relaxed(value, dd->io_base + offset); in atmel_aes_write()
376 static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset, in atmel_aes_read_n() argument
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Domap-aes-gcm.c28 static int omap_aes_gcm_handle_queue(struct omap_aes_dev *dd,
31 static void omap_aes_gcm_finish_req(struct omap_aes_dev *dd, int ret) in omap_aes_gcm_finish_req() argument
33 struct aead_request *req = dd->aead_req; in omap_aes_gcm_finish_req()
35 dd->flags &= ~FLAGS_BUSY; in omap_aes_gcm_finish_req()
36 dd->in_sg = NULL; in omap_aes_gcm_finish_req()
37 dd->out_sg = NULL; in omap_aes_gcm_finish_req()
42 static void omap_aes_gcm_done_task(struct omap_aes_dev *dd) in omap_aes_gcm_done_task() argument
48 alen = ALIGN(dd->assoc_len, AES_BLOCK_SIZE); in omap_aes_gcm_done_task()
49 clen = ALIGN(dd->total, AES_BLOCK_SIZE); in omap_aes_gcm_done_task()
50 rctx = aead_request_ctx(dd->aead_req); in omap_aes_gcm_done_task()
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Datmel-sha.c91 struct atmel_sha_dev *dd; member
115 struct atmel_sha_dev *dd; member
255 static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset) in atmel_sha_read() argument
257 u32 value = readl_relaxed(dd->io_base + offset); in atmel_sha_read()
260 if (dd->flags & SHA_FLAGS_DUMP_REG) { in atmel_sha_read()
263 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value, in atmel_sha_read()
271 static inline void atmel_sha_write(struct atmel_sha_dev *dd, in atmel_sha_write() argument
275 if (dd->flags & SHA_FLAGS_DUMP_REG) { in atmel_sha_write()
278 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value, in atmel_sha_write()
283 writel_relaxed(value, dd->io_base + offset); in atmel_sha_write()
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Domap-sham.c49 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) argument
50 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) argument
51 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) argument
53 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) argument
63 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) argument
65 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) argument
71 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) argument
74 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) argument
88 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) argument
145 struct omap_sham_dev *dd; member
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/drivers/infiniband/hw/qib/
Dqib_iba6120.c306 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, in qib_read_ureg32() argument
309 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg32()
312 if (dd->userbase) in qib_read_ureg32()
314 ((char __iomem *)dd->userbase + in qib_read_ureg32()
315 dd->ureg_align * ctxt)); in qib_read_ureg32()
318 (dd->uregbase + in qib_read_ureg32()
319 (char __iomem *)dd->kregbase + in qib_read_ureg32()
320 dd->ureg_align * ctxt)); in qib_read_ureg32()
332 static inline void qib_write_ureg(const struct qib_devdata *dd, in qib_write_ureg() argument
337 if (dd->userbase) in qib_write_ureg()
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Dqib_twsi.c67 static void i2c_wait_for_writes(struct qib_devdata *dd) in i2c_wait_for_writes() argument
74 dd->f_gpio_mod(dd, 0, 0, 0); in i2c_wait_for_writes()
89 static void scl_out(struct qib_devdata *dd, u8 bit) in scl_out() argument
95 mask = 1UL << dd->gpio_scl_num; in scl_out()
98 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask); in scl_out()
110 if (mask & dd->f_gpio_mod(dd, 0, 0, 0)) in scl_out()
115 qib_dev_err(dd, "SCL interface stuck low > %d uSec\n", in scl_out()
118 i2c_wait_for_writes(dd); in scl_out()
121 static void sda_out(struct qib_devdata *dd, u8 bit) in sda_out() argument
125 mask = 1UL << dd->gpio_sda_num; in sda_out()
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Dqib_init.c103 void qib_set_ctxtcnt(struct qib_devdata *dd) in qib_set_ctxtcnt() argument
106 dd->cfgctxts = dd->first_user_ctxt + num_online_cpus(); in qib_set_ctxtcnt()
107 if (dd->cfgctxts > dd->ctxtcnt) in qib_set_ctxtcnt()
108 dd->cfgctxts = dd->ctxtcnt; in qib_set_ctxtcnt()
109 } else if (qib_cfgctxts < dd->num_pports) in qib_set_ctxtcnt()
110 dd->cfgctxts = dd->ctxtcnt; in qib_set_ctxtcnt()
111 else if (qib_cfgctxts <= dd->ctxtcnt) in qib_set_ctxtcnt()
112 dd->cfgctxts = qib_cfgctxts; in qib_set_ctxtcnt()
114 dd->cfgctxts = dd->ctxtcnt; in qib_set_ctxtcnt()
115 dd->freectxts = (dd->first_user_ctxt > dd->cfgctxts) ? 0 : in qib_set_ctxtcnt()
[all …]
Dqib_tx.c61 void qib_disarm_piobufs(struct qib_devdata *dd, unsigned first, unsigned cnt) in qib_disarm_piobufs() argument
68 spin_lock_irqsave(&dd->pioavail_lock, flags); in qib_disarm_piobufs()
70 __clear_bit(i, dd->pio_need_disarm); in qib_disarm_piobufs()
71 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(i)); in qib_disarm_piobufs()
73 spin_unlock_irqrestore(&dd->pioavail_lock, flags); in qib_disarm_piobufs()
82 struct qib_devdata *dd = rcd->dd; in qib_disarm_piobufs_ifneeded() local
103 spin_lock_irq(&dd->pioavail_lock); in qib_disarm_piobufs_ifneeded()
105 if (__test_and_clear_bit(i, dd->pio_need_disarm)) { in qib_disarm_piobufs_ifneeded()
107 dd->f_sendctrl(rcd->ppd, QIB_SENDCTRL_DISARM_BUF(i)); in qib_disarm_piobufs_ifneeded()
110 spin_unlock_irq(&dd->pioavail_lock); in qib_disarm_piobufs_ifneeded()
[all …]
Dqib_iba7220.c230 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, in qib_read_ureg32() argument
233 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg32()
236 if (dd->userbase) in qib_read_ureg32()
238 ((char __iomem *)dd->userbase + in qib_read_ureg32()
239 dd->ureg_align * ctxt)); in qib_read_ureg32()
242 (dd->uregbase + in qib_read_ureg32()
243 (char __iomem *)dd->kregbase + in qib_read_ureg32()
244 dd->ureg_align * ctxt)); in qib_read_ureg32()
256 static inline void qib_write_ureg(const struct qib_devdata *dd, in qib_write_ureg() argument
261 if (dd->userbase) in qib_write_ureg()
[all …]
Dqib_pcie.c136 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev, in qib_pcie_ddinit() argument
142 dd->pcidev = pdev; in qib_pcie_ddinit()
143 pci_set_drvdata(pdev, dd); in qib_pcie_ddinit()
148 dd->kregbase = ioremap_nocache(addr, len); in qib_pcie_ddinit()
149 if (!dd->kregbase) in qib_pcie_ddinit()
152 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len); in qib_pcie_ddinit()
153 dd->physaddr = addr; /* used for io_remap, etc. */ in qib_pcie_ddinit()
159 dd->pcibar0 = addr; in qib_pcie_ddinit()
160 dd->pcibar1 = addr >> 32; in qib_pcie_ddinit()
161 dd->deviceid = ent->device; /* save for later use */ in qib_pcie_ddinit()
[all …]
Dqib_sd7220.c98 static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc,
100 static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val,
102 static int qib_sd_trimdone_poll(struct qib_devdata *dd);
103 static void qib_sd_trimdone_monitor(struct qib_devdata *dd, const char *where);
104 static int qib_sd_setvals(struct qib_devdata *dd);
105 static int qib_sd_early(struct qib_devdata *dd);
106 static int qib_sd_dactrim(struct qib_devdata *dd);
107 static int qib_internal_presets(struct qib_devdata *dd);
109 static int qib_sd_trimself(struct qib_devdata *dd, int val);
110 static int epb_access(struct qib_devdata *dd, int sdnum, int claim);
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Dqib_iba7322.c162 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ argument
164 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ argument
749 static inline void qib_write_kreg(const struct qib_devdata *dd,
758 static void qib_setup_dca(struct qib_devdata *dd);
759 static void setup_dca_notifier(struct qib_devdata *dd,
761 static void reset_dca_notifier(struct qib_devdata *dd,
775 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, in qib_read_ureg32() argument
778 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg32()
781 (dd->ureg_align * ctxt) + (dd->userbase ? in qib_read_ureg32()
782 (char __iomem *)dd->userbase : in qib_read_ureg32()
[all …]
Dqib_diag.c69 struct qib_devdata *dd; member
78 static struct qib_diag_client *get_client(struct qib_devdata *dd) in get_client() argument
92 dc->dd = dd; in get_client()
104 struct qib_devdata *dd = dc->dd; in return_client() local
108 if (dc == dd->diag_client) { in return_client()
109 dd->diag_client = dc->next; in return_client()
112 tdc = dc->dd->diag_client; in return_client()
124 rdc->dd = NULL; in return_client()
160 int qib_diag_add(struct qib_devdata *dd) in qib_diag_add() argument
173 snprintf(name, sizeof(name), "ipath_diag%d", dd->unit); in qib_diag_add()
[all …]
/drivers/infiniband/hw/hfi1/
Dpcie.c160 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) in hfi1_pcie_ddinit() argument
176 dd_dev_err(dd, "chip PIO range does not match\n"); in hfi1_pcie_ddinit()
180 dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY); in hfi1_pcie_ddinit()
181 if (!dd->kregbase1) { in hfi1_pcie_ddinit()
182 dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); in hfi1_pcie_ddinit()
185 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); in hfi1_pcie_ddinit()
186 dd->chip_rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); in hfi1_pcie_ddinit()
187 dd_dev_info(dd, "RcvArray count: %u\n", dd->chip_rcv_array_count); in hfi1_pcie_ddinit()
188 dd->base2_start = RCV_ARRAY + dd->chip_rcv_array_count * 8; in hfi1_pcie_ddinit()
190 dd->kregbase2 = ioremap_nocache( in hfi1_pcie_ddinit()
[all …]
Dfirmware.c245 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
247 static void dump_fw_version(struct hfi1_devdata *dd);
262 static int __read_8051_data(struct hfi1_devdata *dd, u32 addr, u64 *result) in __read_8051_data() argument
270 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); in __read_8051_data()
272 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, in __read_8051_data()
277 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) in __read_8051_data()
282 dd_dev_err(dd, "timeout reading 8051 data\n"); in __read_8051_data()
289 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA); in __read_8051_data()
298 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result) in read_8051_data() argument
304 spin_lock_irqsave(&dd->dc8051_memlock, flags); in read_8051_data()
[all …]
Dchip.c144 #define emulator_rev(dd) ((dd)->irev >> 8) argument
146 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3) argument
147 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4) argument
1027 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
1028 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
1029 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
1031 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
1033 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
1035 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
1037 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
[all …]
Dinit.c129 static int hfi1_create_kctxt(struct hfi1_devdata *dd, in hfi1_create_kctxt() argument
138 ret = hfi1_create_ctxtdata(ppd, dd->node, &rcd); in hfi1_create_kctxt()
140 dd_dev_err(dd, "Kernel receive context allocation failed\n"); in hfi1_create_kctxt()
159 rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node); in hfi1_create_kctxt()
161 dd_dev_err(dd, "Kernel send context allocation failed\n"); in hfi1_create_kctxt()
172 int hfi1_create_kctxts(struct hfi1_devdata *dd) in hfi1_create_kctxts() argument
177 dd->rcd = kzalloc_node(dd->num_rcv_contexts * sizeof(*dd->rcd), in hfi1_create_kctxts()
178 GFP_KERNEL, dd->node); in hfi1_create_kctxts()
179 if (!dd->rcd) in hfi1_create_kctxts()
182 for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) { in hfi1_create_kctxts()
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Dpio.c63 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl) in __cm_reset() argument
65 write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK); in __cm_reset()
68 sendctrl = read_csr(dd, SEND_CTRL); in __cm_reset()
83 void pio_send_control(struct hfi1_devdata *dd, int op) in pio_send_control() argument
91 spin_lock_irqsave(&dd->sendctrl_lock, flags); in pio_send_control()
93 reg = read_csr(dd, SEND_CTRL); in pio_send_control()
100 for (i = 0; i < ARRAY_SIZE(dd->vld); i++) in pio_send_control()
101 if (!dd->vld[i].mtu) in pio_send_control()
118 __cm_reset(dd, reg); in pio_send_control()
126 dd_dev_err(dd, "%s: invalid control %d\n", __func__, op); in pio_send_control()
[all …]
Daspm.h70 static inline bool aspm_hw_l1_supported(struct hfi1_devdata *dd) in aspm_hw_l1_supported() argument
72 struct pci_dev *parent = dd->pcidev->bus->self; in aspm_hw_l1_supported()
82 pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &dn); in aspm_hw_l1_supported()
89 return (!!dn || is_ax(dd)) && !!up; in aspm_hw_l1_supported()
93 static inline void aspm_hw_set_l1_ent_latency(struct hfi1_devdata *dd) in aspm_hw_set_l1_ent_latency() argument
98 pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, &reg32); in aspm_hw_set_l1_ent_latency()
101 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, reg32); in aspm_hw_set_l1_ent_latency()
104 static inline void aspm_hw_enable_l1(struct hfi1_devdata *dd) in aspm_hw_enable_l1() argument
106 struct pci_dev *parent = dd->pcidev->bus->self; in aspm_hw_enable_l1()
119 pcie_capability_clear_and_set_word(dd->pcidev, PCI_EXP_LNKCTL, in aspm_hw_enable_l1()
[all …]
/drivers/block/mtip32xx/
Dmtip32xx.c124 static int mtip_block_initialize(struct driver_data *dd);
152 struct driver_data *dd = pci_get_drvdata(pdev); in mtip_check_surprise_removal() local
154 if (dd->sr) in mtip_check_surprise_removal()
160 dd->sr = true; in mtip_check_surprise_removal()
161 if (dd->queue) in mtip_check_surprise_removal()
162 set_bit(QUEUE_FLAG_DEAD, &dd->queue->queue_flags); in mtip_check_surprise_removal()
164 dev_warn(&dd->pdev->dev, in mtip_check_surprise_removal()
175 struct driver_data *dd = rq->q->queuedata; in mtip_init_cmd_header() local
179 cmd->command_header = dd->port->command_list + in mtip_init_cmd_header()
181 cmd->command_header_dma = dd->port->command_list_dma + in mtip_init_cmd_header()
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/drivers/clk/ti/
Ddpll3xxx.c52 const struct dpll_data *dd; in _omap3_dpll_write_clken() local
55 dd = clk->dpll_data; in _omap3_dpll_write_clken()
57 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
58 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
59 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
60 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
66 const struct dpll_data *dd; in _omap3_wait_dpll_status() local
71 dd = clk->dpll_data; in _omap3_wait_dpll_status()
74 state <<= __ffs(dd->idlest_mask); in _omap3_wait_dpll_status()
76 while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) in _omap3_wait_dpll_status()
[all …]
/drivers/parport/
Dparport_ax88796.c58 struct ax_drvdata *dd = pp_to_drv(p); in parport_ax88796_read_data() local
60 return readb(dd->spp_data); in parport_ax88796_read_data()
66 struct ax_drvdata *dd = pp_to_drv(p); in parport_ax88796_write_data() local
68 writeb(data, dd->spp_data); in parport_ax88796_write_data()
74 struct ax_drvdata *dd = pp_to_drv(p); in parport_ax88796_read_control() local
75 unsigned int cpr = readb(dd->spp_cpr); in parport_ax88796_read_control()
96 struct ax_drvdata *dd = pp_to_drv(p); in parport_ax88796_write_control() local
97 unsigned int cpr = readb(dd->spp_cpr); in parport_ax88796_write_control()
113 dev_dbg(dd->dev, "write_control: ctrl=%02x, cpr=%02x\n", control, cpr); in parport_ax88796_write_control()
114 writeb(cpr, dd->spp_cpr); in parport_ax88796_write_control()
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