| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | smu7_hwmgr.c | 627 &data->dpm_table.sclk_table, in smu7_reset_dpm_tables()
685 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v0()
688 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
690 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
692 …data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 … in smu7_setup_dpm_tables_v0()
693 data->dpm_table.sclk_table.count++; in smu7_setup_dpm_tables_v0()
779 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v1()
781 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
784 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v1()
787 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
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| D | process_pptables_v1_0.c | 423 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; in get_sclk_voltage_dependency_table() local
437 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
439 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
442 memset(sclk_table, 0x00, table_size); in get_sclk_voltage_dependency_table()
444 sclk_table->count = (uint32_t)tonga_table->ucNumEntries; in get_sclk_voltage_dependency_table()
452 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
471 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
473 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
476 memset(sclk_table, 0x00, table_size); in get_sclk_voltage_dependency_table()
478 sclk_table->count = (uint32_t)polaris_table->ucNumEntries; in get_sclk_voltage_dependency_table()
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| D | smu7_hwmgr.h | 109 struct smu7_single_dpm_table sclk_table; member
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| D | vega10_hwmgr.c | 3317 struct vega10_single_dpm_table *sclk_table = in vega10_find_dpm_states_clocks_in_dpm_table() local
3335 for (i = 0; i < sclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3336 if (sclk == sclk_table->dpm_levels[i].value) in vega10_find_dpm_states_clocks_in_dpm_table()
3341 DPMTABLE_OD_UPDATE_SCLK) && i >= sclk_table->count) { in vega10_find_dpm_states_clocks_in_dpm_table()
3360 for (i = 0; i < sclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3361 if (sclk == sclk_table->dpm_levels[i].value) in vega10_find_dpm_states_clocks_in_dpm_table()
3365 if (i >= sclk_table->count) in vega10_find_dpm_states_clocks_in_dpm_table()
4693 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_print_clock_levels() local
4712 for (i = 0; i < sclk_table->count; i++) in vega10_print_clock_levels()
4714 i, sclk_table->dpm_levels[i].value / 100, in vega10_print_clock_levels()
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| D | cz_hwmgr.c | 1764 struct phm_clock_voltage_dependency_table *sclk_table = in cz_print_clock_levels() local
1776 for (i = 0; i < sclk_table->count; i++) in cz_print_clock_levels()
1778 i, sclk_table->entries[i].clk / 100, in cz_print_clock_levels()
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| /drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | polaris10_smc.c | 777 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
780 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
796 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels()
798 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in polaris10_populate_all_graphic_levels()
806 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
831 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1211 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters()
1214 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
1300 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in polaris10_populate_smc_boot_level()
1363 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = in polaris10_populate_clock_stretcher_data_table() local
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| D | fiji_smc.c | 797 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels()
799 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
814 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
818 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels()
820 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in fiji_populate_all_graphic_levels()
827 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
852 for (i = 2; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1105 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1360 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters()
1363 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
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| D | tonga_smc.c | 622 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
624 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
639 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels()
640 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
644 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels()
646 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in tonga_populate_all_graphic_levels()
653 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
683 for (i = 2; i < dpm_table->sclk_table.count; i++) in tonga_populate_all_graphic_levels()
1464 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters()
1467 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
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| D | iceland_smc.c | 837 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
839 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
854 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
855 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
859 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels()
861 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in iceland_populate_all_graphic_levels()
884 for (i = 2; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
1506 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters()
1509 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1542 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in iceland_populate_smc_boot_level()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | ci_dpm.c | 2683 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2686 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
3424 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3426 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3433 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3439 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3441 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3597 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3612 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3615 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
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| D | ci_dpm.h | 69 struct ci_single_dpm_table sclk_table; member
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| /drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 2531 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2534 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
3265 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3267 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3274 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3280 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3282 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3440 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3455 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3458 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
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| D | ci_dpm.h | 68 struct ci_single_dpm_table sclk_table; member
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