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Searched refs:ACACHE_BSRAM (Results 1 – 10 of 10) sorted by relevance

/arch/blackfin/mach-bf533/include/mach/
Dmem_map.h54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
92 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
126 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf537/include/mach/
Dmem_map.h51 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
87 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
123 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf527/include/mach/
Dmem_map.h49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf518/include/mach/
Dmem_map.h49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf538/include/mach/
Dmem_map.h53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf548/include/mach/
Dmem_map.h53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf609/include/mach/
Dmem_map.h61 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf561/include/mach/
Dmem_map.h56 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/include/asm/
Ddef_LPBlackfin.h555 #define ACACHE_BSRAM 0x00000008 macro
/arch/blackfin/kernel/
Dsetup.c1334 case ACACHE_BSRAM: