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Searched refs:DMEM_CNTR (Results 1 – 9 of 9) sorted by relevance

/arch/blackfin/mach-bf537/include/mach/
Dmem_map.h51 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
57 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
65 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
87 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
94 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
102 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
123 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
130 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
138 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
/arch/blackfin/mach-bf533/include/mach/
Dmem_map.h54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
60 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
68 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
92 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
99 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
107 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
126 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
131 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
/arch/blackfin/mach-bf527/include/mach/
Dmem_map.h49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
55 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
63 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
/arch/blackfin/mach-bf518/include/mach/
Dmem_map.h49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
55 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
63 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
/arch/blackfin/mach-bf538/include/mach/
Dmem_map.h53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
59 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
67 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
/arch/blackfin/mach-bf548/include/mach/
Dmem_map.h53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
59 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
67 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
/arch/blackfin/mach-bf609/include/mach/
Dmem_map.h61 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
67 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
75 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
/arch/blackfin/mach-bf561/include/mach/
Dmem_map.h56 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro
62 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro
70 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
/arch/blackfin/mach-common/
Dcache-c.c81 (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0))); in bfin_dcache_init()