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Searched refs:PORT_PREF0 (Results 1 – 10 of 10) sorted by relevance

/arch/blackfin/mach-bf537/include/mach/
Dmem_map.h51 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
57 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
65 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
87 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
94 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
102 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
123 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
130 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
138 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf533/include/mach/
Dmem_map.h54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
60 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
68 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
92 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
99 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
107 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
126 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
131 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf527/include/mach/
Dmem_map.h49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
55 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
63 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf518/include/mach/
Dmem_map.h49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
55 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
63 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf538/include/mach/
Dmem_map.h53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
59 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
67 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf548/include/mach/
Dmem_map.h53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
59 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
67 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf609/include/mach/
Dmem_map.h61 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
67 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
75 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf561/include/mach/
Dmem_map.h56 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
62 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
70 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-common/
Dcache-c.c81 (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0))); in bfin_dcache_init()
/arch/blackfin/include/asm/
Ddef_LPBlackfin.h558 #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ macro