Searched refs:DMEM_CNTR (Results 1 – 9 of 9) sorted by relevance
51 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro57 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro65 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro87 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro94 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro102 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro123 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro130 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro138 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro60 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro68 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro92 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro99 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro107 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro126 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro131 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro55 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro63 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro59 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro67 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
61 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro67 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro75 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
56 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) macro62 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) macro70 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) macro
81 (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0))); in bfin_dcache_init()