Searched refs:NR_IRQS_LEGACY (Results 1 – 19 of 19) sorted by relevance
82 #define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)83 #define MX1_INT_CSI (NR_IRQS_LEGACY + 6)84 #define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)85 #define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)86 #define MX1_COMP_INT (NR_IRQS_LEGACY + 9)87 #define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)88 #define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)89 #define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)90 #define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)91 #define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)[all …]
132 #define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)133 #define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)134 #define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)135 #define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)136 #define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)137 #define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)138 #define MX27_INT_MSHC (NR_IRQS_LEGACY + 7)139 #define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)140 #define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)141 #define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)[all …]
103 #define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)104 #define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)105 #define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)106 #define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)107 #define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)108 #define MX21_INT_I2C (NR_IRQS_LEGACY + 12)109 #define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)110 #define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)111 #define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)112 #define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)[all …]
72 #define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)73 #define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)74 #define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)75 #define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)76 #define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)77 #define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)78 #define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)79 #define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)80 #define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)81 #define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)[all …]
124 #define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)125 #define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)126 #define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)127 #define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)128 #define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)129 #define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)130 #define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)131 #define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)132 #define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)133 #define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)[all …]
125 #define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)126 #define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)127 #define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)128 #define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)129 #define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)130 #define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)131 #define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)132 #define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)133 #define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)134 #define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)[all …]
147 #define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)148 #define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)149 #define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)150 #define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)151 #define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)152 #define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)153 #define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)154 #define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)155 #define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)156 #define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)[all …]
37 #define INT_CAMERA (NR_IRQS_LEGACY + 1)38 #define INT_FIQ (NR_IRQS_LEGACY + 3)39 #define INT_RTDX (NR_IRQS_LEGACY + 6)40 #define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7)41 #define INT_HOST (NR_IRQS_LEGACY + 8)42 #define INT_ABORT (NR_IRQS_LEGACY + 9)43 #define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13)44 #define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14)45 #define INT_UART3 (NR_IRQS_LEGACY + 15)46 #define INT_TIMER3 (NR_IRQS_LEGACY + 16)[all …]
4 #define NR_IRQS_LEGACY 16 macro9 #define NR_IRQS NR_IRQS_LEGACY44 return NR_IRQS_LEGACY; in nr_legacy_irqs()
131 #define NR_IRQS_LEGACY 16 macro146 #define NR_IRQS NR_IRQS_LEGACY
146 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))206 #define gsi_top (NR_IRQS_LEGACY)
26 #define NR_IRQS_LEGACY 1 macro
30 #define NR_IRQS_LEGACY NUM_ISA_INTERRUPTS macro
18 #define PXA_IRQ(x) (NR_IRQS_LEGACY + (x))
236 omap_l2_irq -= NR_IRQS_LEGACY; in omap1_init_irq()
408 .nr_legacy_irqs = NR_IRQS_LEGACY,
107 static u32 isa_irq_to_gsi[NR_IRQS_LEGACY] __read_mostly = {333 if (bus_irq >= NR_IRQS_LEGACY) { in mp_override_legacy_irq()466 if (bus_irq < NR_IRQS_LEGACY) in acpi_sci_ioapic_setup()
36 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];393 if (gsi_top <= NR_IRQS_LEGACY) in arch_probe_nr_irqs()
486 for (irq = 0; irq < NR_IRQS_LEGACY; irq++) { in pci_xen_initial_domain()