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Searched refs:radeon_ring_write (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/radeon/
Dcik_sdma.c144 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); in cik_sdma_ring_ib_execute()
145 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_sdma_ring_ib_execute()
146 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_sdma_ring_ib_execute()
147 radeon_ring_write(ring, 1); /* number of DWs to follow */ in cik_sdma_ring_ib_execute()
148 radeon_ring_write(ring, next_rptr); in cik_sdma_ring_ib_execute()
153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); in cik_sdma_ring_ib_execute()
154 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_ib_execute()
155 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_ib_execute()
156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
157 radeon_ring_write(ring, ib->length_dw); in cik_sdma_ring_ib_execute()
[all …]
Duvd_v2_2.c45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit()
46 radeon_ring_write(ring, fence->seq); in uvd_v2_2_fence_emit()
47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit()
48 radeon_ring_write(ring, lower_32_bits(addr)); in uvd_v2_2_fence_emit()
49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit()
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v2_2_fence_emit()
51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit()
52 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit()
55 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
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Devergreen_dma.c47 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); in evergreen_dma_fence_ring_emit()
48 radeon_ring_write(ring, addr & 0xfffffffc); in evergreen_dma_fence_ring_emit()
49 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
50 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
52 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); in evergreen_dma_fence_ring_emit()
54 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0)); in evergreen_dma_fence_ring_emit()
55 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); in evergreen_dma_fence_ring_emit()
56 radeon_ring_write(ring, 1); in evergreen_dma_fence_ring_emit()
77 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1)); in evergreen_dma_ring_ib_execute()
78 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in evergreen_dma_ring_ib_execute()
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Duvd_v1_0.c87 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit()
88 radeon_ring_write(ring, addr & 0xffffffff); in uvd_v1_0_fence_emit()
89 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit()
90 radeon_ring_write(ring, fence->seq); in uvd_v1_0_fence_emit()
91 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v1_0_fence_emit()
92 radeon_ring_write(ring, 0); in uvd_v1_0_fence_emit()
94 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit()
95 radeon_ring_write(ring, 0); in uvd_v1_0_fence_emit()
96 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit()
97 radeon_ring_write(ring, 0); in uvd_v1_0_fence_emit()
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Dsi_dma.c191 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); in si_dma_vm_flush()
193 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2)); in si_dma_vm_flush()
195 …radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> … in si_dma_vm_flush()
197 radeon_ring_write(ring, pd_addr >> 12); in si_dma_vm_flush()
200 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); in si_dma_vm_flush()
201 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); in si_dma_vm_flush()
202 radeon_ring_write(ring, 1); in si_dma_vm_flush()
205 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); in si_dma_vm_flush()
206 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); in si_dma_vm_flush()
207 radeon_ring_write(ring, 1 << vm_id); in si_dma_vm_flush()
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Dr600_dma.c254 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); in r600_dma_ring_test()
255 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
256 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
257 radeon_ring_write(ring, 0xDEADBEEF); in r600_dma_ring_test()
294 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); in r600_dma_fence_ring_emit()
295 radeon_ring_write(ring, addr & 0xfffffffc); in r600_dma_fence_ring_emit()
296 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit()
297 radeon_ring_write(ring, lower_32_bits(fence->seq)); in r600_dma_fence_ring_emit()
299 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); in r600_dma_fence_ring_emit()
321 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); in r600_dma_semaphore_ring_emit()
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Dni_dma.c133 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); in cayman_dma_ring_ib_execute()
134 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cayman_dma_ring_ib_execute()
135 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in cayman_dma_ring_ib_execute()
136 radeon_ring_write(ring, next_rptr); in cayman_dma_ring_ib_execute()
143 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); in cayman_dma_ring_ib_execute()
144 radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0)); in cayman_dma_ring_ib_execute()
145 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in cayman_dma_ring_ib_execute()
146 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
452 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); in cayman_dma_vm_flush()
453 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2)); in cayman_dma_vm_flush()
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Dr300.c216 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); in r300_fence_ring_emit()
217 radeon_ring_write(ring, 0); in r300_fence_ring_emit()
218 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); in r300_fence_ring_emit()
219 radeon_ring_write(ring, 0); in r300_fence_ring_emit()
221 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_fence_ring_emit()
222 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); in r300_fence_ring_emit()
223 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); in r300_fence_ring_emit()
224 radeon_ring_write(ring, R300_ZC_FLUSH); in r300_fence_ring_emit()
226 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_fence_ring_emit()
227 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | in r300_fence_ring_emit()
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Duvd_v3_1.c47 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v3_1_semaphore_emit()
48 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); in uvd_v3_1_semaphore_emit()
50 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v3_1_semaphore_emit()
51 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); in uvd_v3_1_semaphore_emit()
53 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v3_1_semaphore_emit()
54 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); in uvd_v3_1_semaphore_emit()
Dni.c1415 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1416 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); in cayman_fence_ring_emit()
1417 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_fence_ring_emit()
1418 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1419 radeon_ring_write(ring, 10); /* poll interval */ in cayman_fence_ring_emit()
1421 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1422 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in cayman_fence_ring_emit()
1423 radeon_ring_write(ring, lower_32_bits(addr)); in cayman_fence_ring_emit()
1424 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
1425 radeon_ring_write(ring, fence->seq); in cayman_fence_ring_emit()
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Drv515.c70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
71 radeon_ring_write(ring, in rv515_ring_start()
76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
77 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); in rv515_ring_start()
78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
79 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); in rv515_ring_start()
80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
81 radeon_ring_write(ring, 0); in rv515_ring_start()
82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
83 radeon_ring_write(ring, 0); in rv515_ring_start()
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Drv770_dma.c74 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); in rv770_copy_dma()
75 radeon_ring_write(ring, dst_offset & 0xfffffffc); in rv770_copy_dma()
76 radeon_ring_write(ring, src_offset & 0xfffffffc); in rv770_copy_dma()
77 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in rv770_copy_dma()
78 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in rv770_copy_dma()
Dradeon_vce.c702 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE)); in radeon_vce_semaphore_emit()
703 radeon_ring_write(ring, cpu_to_le32((addr >> 3) & 0x000FFFFF)); in radeon_vce_semaphore_emit()
704 radeon_ring_write(ring, cpu_to_le32((addr >> 23) & 0x000FFFFF)); in radeon_vce_semaphore_emit()
705 radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0))); in radeon_vce_semaphore_emit()
707 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END)); in radeon_vce_semaphore_emit()
722 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB)); in radeon_vce_ib_execute()
723 radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr)); in radeon_vce_ib_execute()
724 radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr))); in radeon_vce_ib_execute()
725 radeon_ring_write(ring, cpu_to_le32(ib->length_dw)); in radeon_vce_ib_execute()
741 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE)); in radeon_vce_fence_emit()
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Dr600.c2697 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2698 radeon_ring_write(ring, 0x1); in r600_cp_start()
2700 radeon_ring_write(ring, 0x0); in r600_cp_start()
2701 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2703 radeon_ring_write(ring, 0x3); in r600_cp_start()
2704 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2706 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in r600_cp_start()
2707 radeon_ring_write(ring, 0); in r600_cp_start()
2708 radeon_ring_write(ring, 0); in r600_cp_start()
2842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
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Dcik.c3504 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3505 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_test()
3506 radeon_ring_write(ring, 0xDEADBEEF); in cik_ring_test()
3560 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3561 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in cik_hdp_flush_cp_ring_emit()
3564 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2); in cik_hdp_flush_cp_ring_emit()
3565 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2); in cik_hdp_flush_cp_ring_emit()
3566 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3567 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3568 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_hdp_flush_cp_ring_emit()
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Dr200.c105 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
106 radeon_ring_write(ring, (1 << 16)); in r200_copy_dma()
113 radeon_ring_write(ring, PACKET0(0x720, 2)); in r200_copy_dma()
114 radeon_ring_write(ring, src_offset); in r200_copy_dma()
115 radeon_ring_write(ring, dst_offset); in r200_copy_dma()
116 radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); in r200_copy_dma()
120 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
121 radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE); in r200_copy_dma()
Dsi.c3373 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3374 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_fence_ring_emit()
3375 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3376 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3377 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in si_fence_ring_emit()
3381 radeon_ring_write(ring, 0xFFFFFFFF); in si_fence_ring_emit()
3382 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3383 radeon_ring_write(ring, 10); /* poll interval */ in si_fence_ring_emit()
3385 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
3386 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); in si_fence_ring_emit()
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Dr100.c843 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_ring_hdp_flush()
844 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | in r100_ring_hdp_flush()
846 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_ring_hdp_flush()
847 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); in r100_ring_hdp_flush()
859 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); in r100_fence_ring_emit()
860 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); in r100_fence_ring_emit()
861 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); in r100_fence_ring_emit()
862 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); in r100_fence_ring_emit()
864 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r100_fence_ring_emit()
865 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); in r100_fence_ring_emit()
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Dr420.c219 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); in r420_cp_errata_init()
220 radeon_ring_write(ring, rdev->config.r300.resync_scratch); in r420_cp_errata_init()
221 radeon_ring_write(ring, 0xDEADBEEF); in r420_cp_errata_init()
233 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r420_cp_errata_fini()
234 radeon_ring_write(ring, R300_RB3D_DC_FINISH); in r420_cp_errata_fini()
Devergreen.c3029 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in evergreen_ring_ib_execute()
3030 radeon_ring_write(ring, 1); in evergreen_ring_ib_execute()
3034 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in evergreen_ring_ib_execute()
3035 radeon_ring_write(ring, ((ring->rptr_save_reg - in evergreen_ring_ib_execute()
3037 radeon_ring_write(ring, next_rptr); in evergreen_ring_ib_execute()
3040 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in evergreen_ring_ib_execute()
3041 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in evergreen_ring_ib_execute()
3042 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); in evergreen_ring_ib_execute()
3043 radeon_ring_write(ring, next_rptr); in evergreen_ring_ib_execute()
3044 radeon_ring_write(ring, 0); in evergreen_ring_ib_execute()
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Dradeon_ring.c174 radeon_ring_write(ring, ring->nop); in radeon_ring_commit()
355 radeon_ring_write(ring, data[i]); in radeon_ring_restore()
Dradeon.h2708 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) in radeon_ring_write() function