| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 54 minimum: 0
55 maximum: 0xf
60 minimum: 0
61 maximum: 0xf
66 minimum: 0
67 maximum: 0xf
72 minimum: 0
73 maximum: 0xf
78 minimum: 0
79 maximum: 0xf
[all …]
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| D | marvell,xenon-sdhci.txt | 40 SDHC System Operation Control Register Bit[7:0].
61 Valid range = [0:0x1F].
62 ZNR is set as 0xF by default if this property is not provided.
67 Valid range = [0:0x1F].
68 ZPR is set as 0xF by default if this property is not provided.
74 Set as 0x4 by default if this property is not provided.
92 be set as 0x9 in driver.
109 reg = <0xaa0000 0x1000>;
127 reg = <0xab0000 0x1000>;
141 reg = <0xaa0000 0x1000>,
[all …]
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| /Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 13 * Bits [2:0] are the Function number.
67 reg = <0xa 0x1>;
74 reg = <0xf 0x1>;
82 msi-map = <0x0 &msi_a 0x0 0x10000>,
95 reg = <0xa 0x1>;
102 reg = <0xf 0x1>;
110 msi-map = <0x0 &msi_a 0x0 0x100>,
111 msi-map-mask = <0xff>
124 reg = <0xa 0x1>;
131 reg = <0xf 0x1>;
[all …]
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| D | pci-iommu.txt | 13 * Bits [2:0] are the Function number.
56 reg = <0xa 0x1>;
62 reg = <0xf 0x1>;
70 iommu-map = <0x0 &iommu 0x0 0x10000>;
83 reg = <0xa 0x1>;
89 reg = <0xf 0x1>;
97 iommu-map = <0x0 &iommu 0x0 0x10000>;
98 iommu-map-mask = <0xfff8>;
111 reg = <0xa 0x1>;
117 reg = <0xf 0x1>;
[all …]
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| D | ti,j721e-pci-host.yaml | 48 const: 0x104c
51 const: 0xb00d
88 reg = <0x00 0x02900000 0x00 0x1000>,
89 <0x00 0x02907000 0x00 0x400>,
90 <0x00 0x0d000000 0x00 0x00800000>,
91 <0x00 0x10000000 0x00 0x00001000>;
102 bus-range = <0x0 0xf>;
103 vendor-id = <0x104c>;
104 device-id = <0xb00d>;
105 msi-map = <0x0 &gic_its 0x0 0x10000>;
[all …]
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| /Documentation/arm/ |
| D | vlocks.rst | 33 int currently_voting[NR_CPUS] = { 0, };
42 currently_voting[this_cpu] = 0;
48 currently_voting[this_cpu] = 0;
52 while (currently_voting[i] != 0)
100 my_town = towns[(this_cpu >> 4) & 0xf];
101 I_won = vlock_trylock(my_town, this_cpu & 0xf);
104 my_state = states[(this_cpu >> 8) & 0xf];
105 I_won = vlock_lock(my_state, this_cpu & 0xf));
108 I_won = vlock_lock(the_whole_country, this_cpu & 0xf];
134 CMP Rt, #0
[all …]
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| /Documentation/devicetree/bindings/soc/bcm/ |
| D | brcm,bcm2835-vchiq.txt | 15 reg = <0x7e00b840 0xf>;
16 interrupts = <0 2>;
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| /Documentation/devicetree/bindings/net/ieee802154/ |
| D | at86rf230.txt | 16 arrays of xtal pins: 0 = +0 pF, 0xf = +4.5 pF
20 at86rf231@0 {
23 reg = <0>;
26 xtal-trim = /bits/ 8 <0x06>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-single.txt | 32 pinctrl-single,power-source = <0x30 0xf0>;
38 pinctrl-single,bias-pullup = <0 1 0 1>;
44 pinctrl-single,bias-pulldown = <2 2 0 2>;
61 pinctrl-single,input-schmitt = <0x30 0x70>;
67 pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
74 pinctrl-single,low-power-mode = <0x288 0x388>;
83 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
102 pinctrl-single,pins = <0xdc 0x118>;
104 Where 0xdc is the offset from the pinctrl register base address for the device
105 pinctrl register, and 0x118 contains the desired value of the pinctrl register.
[all …]
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | imx-cpufreq-dt.txt | 15 0: Consumer
27 /* grade >= 0, consumer only */
28 opp-supported-hw = <0xf>, <0x3>;
35 opp-supported-hw = <0xe>, <0x7>;
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| /Documentation/devicetree/bindings/soc/fsl/ |
| D | bman-portals.txt | 44 ranges = <0 0xf 0xf4000000 0x200000>;
46 bman-portal@0 {
47 compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
48 reg = <0x0 0x4000>, <0x100000 0x1000>;
49 interrupts = <105 2 0 0>;
52 compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
53 reg = <0x4000 0x4000>, <0x101000 0x1000>;
54 interrupts = <107 2 0 0>;
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| D | qman-portals.txt | 92 ranges = <0 0xf 0xf4200000 0x200000>;
94 qman-portal@0 {
95 compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
96 reg = <0 0x4000>, <0x100000 0x1000>;
97 interrupts = <104 2 0 0>;
99 fsl,qman-channel-id = <0>;
102 fsl,liodn = <0x21>;
106 fsl,liodn = <0xa1>;
110 fsl,liodn = <0x41 0x66>;
115 compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
[all …]
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| /Documentation/devicetree/bindings/spmi/ |
| D | spmi.yaml | 34 const: 0
37 "@[0-9a-f]$":
46 - minimum: 0
47 maximum: 0xf
48 - enum: [ 0 ]
50 0 means user ID address. 1 is reserved for group ID address.
64 spmi@0 {
65 reg = <0 0>;
68 #size-cells = <0>;
70 child@0 {
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | cs35l33.txt | 22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
31 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
39 ADC data word. This property can be set as a value of 0 for bits 15 down
40 to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.
54 LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
64 0xF).
72 from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
85 tracking. This property can be set to values from 0 to 3 with rates of 128
90 using VPMON. This property can be set to values from 0 to 6 starting at
[all …]
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| /Documentation/devicetree/bindings/bus/ |
| D | mvebu-mbus.txt | 65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | snps,dwmac.yaml | 164 * snps,priority, RX queue priority (Range 0x0 to 0xF)
184 [Attention] Queue 0 is reserved for legacy traffic
191 * snps,priority, TX queue priority (Range 0x0 to 0xF)
364 snps,wr_osr_lmt = <0xf>;
365 snps,rd_osr_lmt = <0xf>;
366 snps,blen = <256 128 64 32 0 0 0>;
374 snps,map-to-dma-channel = <0x0>;
375 snps,priority = <0x0>;
383 snps,weight = <0x10>;
385 snps,priority = <0x0>;
[all …]
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| /Documentation/driver-api/ |
| D | connector.rst | 53 __u8 data[0];
121 l_local.nl_pid = 0;
136 option with the NETLINK_DROP_MEMBERSHIP parameter which is defined as 0.
140 In case of connector it is CN_NETLINK_USERS + 0xf, so if you want to use
142 Additional 0xf numbers are allocated to be used by non-in-kernel users.
144 Due to this limitation, group 0xffffffff does not work now, so one can
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| /Documentation/devicetree/bindings/mfd/ |
| D | bd9571mwv.txt | 28 - rohm,ddr-backup-power : Value to use for DDR-Backup Power (default 0).
32 - bit 0: DDR0
50 reg = <0x30>;
52 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
57 rohm,ddr-backup-power = <0xf>;
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| /Documentation/devicetree/bindings/thermal/ |
| D | zx2967-thermal.txt | 11 - #thermal-sensor-cells: must be 0.
20 reg = <0x0148a000 0x20>;
23 #thermal-sensor-cells = <0>;
31 cpumask = <0xf>;
37 cpumask = <0x30>;
50 thermal-sensors = <&tempsensor 0>;
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| /Documentation/fault-injection/ |
| D | nvme-fault-injection.rst | 33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | apm-xgene-phy.txt | 10 the mode of the PHY. Possible values are 0 (SATA),
20 supported link speed on the host. Range from 0 to
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
26 supported link speed on the host. Default is 0.
30 between 0 to 31 in unit of dB. Default is 3.
33 Range is between 0 to 199500 in unit of uV.
37 speed on the host. Range is 0 to 273000 in unit of
38 uV. Default is 0.
41 speed on the host. Range is 0 to 127400 in unit uV.
42 Default is 0x0.
[all …]
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | srio.txt | 9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
20 be set to 0x11000.
83 reg = <0xf 0xfe0c0000 0 0x11000>;
94 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
102 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | ti-tsc-adc.txt | 30 AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7.
31 XP = 0, XN = 1, YP = 2, YN = 3.
37 AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7.
46 event. Start from a lower value, say 0x400, and
60 Maximum value is 0x3FFFF.
66 Maximum value is 0xFF.
71 by ADC to generate a sample. Valid range is 0
81 ti,wire-config = <0x00 0x11 0x22 0x33>;
82 ti,charge-delay = <0x400>;
87 ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>;
[all …]
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| /Documentation/arm/samsung/ |
| D | clksrc-change-registers.awk | 26 p[0] = tp[2]
32 if (0)
35 if (f ~ /0x1/)
37 else if (f ~ /0x3/)
39 else if (f ~ /0x7/)
41 else if (f ~ /0xf/)
51 if (id <= 0) {
69 while (getline line < ARGV[1] > 0) {
73 name = fields[0]
74 if (0)
[all …]
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