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| /Documentation/driver-api/serial/ |
| D | driver.rst | 17 The low level serial hardware driver is responsible for supplying port
20 responsible for handling interrupts for the port, and providing any
28 the correct port structure (via uart_get_console) and decoding command line
41 necessary locking using port->lock. There are some exceptions (which
44 There are two locks. A per-port spinlock, and an overall semaphore.
46 From the core driver perspective, the port->lock locks the following
49 port->mctrl
50 port->icount
51 port->state->xmit.head (circ_buf->head)
52 port->state->xmit.tail (circ_buf->tail)
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | mt7530.txt | 34 - reg: Port address described must be 6 for CPU port and from 0 to 5 for
36 - phy-mode: String, the following values are acceptable for port labeled
43 Port 5 of mt7530 and mt7621 switch is muxed between:
45 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
46 of the SOC. Used in many setups where port 0/4 becomes the WAN port.
51 Port 5 modes/configurations:
52 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
54 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
56 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
57 It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
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| D | ocelot.txt | 29 The CPU port property ("ethernet") configures the feature called "NPI port" in
30 the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are
31 connected, in the Node Processor Interface (NPI) mode, to an Ethernet port.
32 By default, in fsl-ls1028a.dtsi, the NPI port is assigned to the internal
33 2.5Gbps port@4, but can be moved to the 1Gbps port@5, depending on the specific
34 use case. Moving the NPI port to an external switch port is hardware possible,
37 tagging) is supported on a single port at a time.
39 Any port can be disabled (and in fsl-ls1028a.dtsi, they are indeed all disabled
41 switch port is enabled at all, the ENETC PF2 (enetc_port2) should be enabled as
44 in hardware truly belong to the ENETC port #2 and not to Felix.
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| D | qca8k.txt | 20 mdio-bus each subnode describing a port needs to have a valid phandle
22 N:N mapping of port and PHY id.
27 The CPU port of this switch is always port 0.
29 A CPU port node has the following optional node:
79 port@0 {
90 port@1 {
96 port@2 {
102 port@3 {
108 port@4 {
114 port@5 {
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| D | lan9303.txt | 1 SMSC/MicroChip LAN9303 three port ethernet switch
19 described in dsa/dsa.txt. The CPU port of this switch is always port 0.
47 port@0 { /* RMII fixed link to master */
53 port@1 { /* external port 1 */
58 port@2 { /* external port 2 */
84 port@0 {
90 port@1 { /* external port 1 */
95 port@2 { /* external port 2 */
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| D | vitesse,vsc73xx.txt | 9 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
10 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
11 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
12 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
60 port@0 {
64 port@1 {
68 port@2 {
72 port@3 {
76 vsc: port@6 {
102 port@0 {
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| /Documentation/devicetree/bindings/net/ |
| D | hisilicon-hns-nic.txt | 10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
11 connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They
17 port-id can be 2 to 7. Here is the diagram:
23 port port
28 this switch. In this case, the port-id will be 2 only.
32 | | service| port(2)
34 port | switch |
37 external port
42 - port-idx-in-ae: is the index of port provided by AE.
44 to the CPU. The port-idx-in-ae can be 0 to 5. Here is the diagram:
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| D | hisilicon-hns-dsaf.txt | 8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
18 serdes-syscon in port node does not exist). It is recommended using
22 single-port mode.
26 - phy-handle: phy handle of physical port, 0 if not any phy device. It is optional
27 attribute. If port node exists, phy-handle in each port node will be used.
35 - port: subnodes of dsaf. A dsaf node may contain several port nodes(Depending
36 on mode of dsaf). Port node contain some attributes listed below:
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| D | marvell-orion-net.txt | 10 describes up to 3 ethernet port nodes within that controller. The reason for
11 the multiple levels is that the port registers are interleaved within a single
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
32 * Ethernet port node
34 Required port properties:
35 - compatible: shall be one of "marvell,orion-eth-port",
36 "marvell,kirkwood-eth-port".
37 - reg: port number relative to ethernet controller, shall be 0, 1, or 2.
38 - interrupts: port interrupt.
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| D | cortina,gemini-ethernet.txt | 23 - port0: contains the resources for ethernet port 0
24 - port1: contains the resources for ethernet port 1
27 - compatible: must be "cortina,gemini-ethernet-port"
29 the GMAC memory area of the port
30 - interrupts: should contain the interrupt line of the port.
33 the port.
35 clocking the silicon in this port
67 gmac0: ethernet-port@0 {
68 compatible = "cortina,gemini-ethernet-port";
69 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
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| D | fsl-fman.txt | 6 - FMan Port Node
154 FMan Port Node
170 - "fsl,fman-v2-port-oh" for FManV2 OH ports
171 - "fsl,fman-v2-port-rx" for FManV2 RX ports
172 - "fsl,fman-v2-port-tx" for FManV2 TX ports
173 - "fsl,fman-v3-port-oh" for FManV3 OH ports
174 - "fsl,fman-v3-port-rx" for FManV3 RX ports
175 - "fsl,fman-v3-port-tx" for FManV3 TX ports
180 Definition: Specifies the hardware port id.
181 Each hardware port on the FMan has its own hardware PortID.
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| /Documentation/PCI/ |
| D | pciebus-howto.rst | 5 The PCI Express Port Bus Driver Guide HOWTO
14 This guide describes the basics of the PCI Express Port Bus driver
16 register/unregister with the PCI Express Port Bus Driver.
19 What is the PCI Express Port Bus Driver
22 A PCI Express Port is a logical PCI-PCI Bridge structure. There
23 are two types of PCI Express Port: the Root Port and the Switch
24 Port. The Root Port originates a PCI Express link from a PCI Express
25 Root Complex and the Switch Port connects PCI Express links to
26 internal logical PCI buses. The Switch Port, which has its secondary
28 switch's Upstream Port. The switch's Downstream Port is bridging from
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| /Documentation/ABI/testing/ |
| D | sysfs-class-typec | 1 USB Type-C port devices (eg. /sys/class/typec/port0/)
3 What: /sys/class/typec/<port>/data_role
8 requesting data role swapping on the port. Swapping is supported
13 KOBJ_CHANGE on the port. The current role is show in brackets,
14 for example "[host] device" when DRP port is in host mode.
18 What: /sys/class/typec/<port>/power_role
23 power role swap on the port. Swapping is supported as
33 What: /sys/class/typec/<port>/port_type
37 Indicates the type of the port. This attribute can be used for
38 requesting a change in the port type. Port type change is
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| /Documentation/devicetree/bindings/ |
| D | graph.txt | 24 the connecting data buses. A single port with multiple connections can
30 Ports are described by child 'port' nodes contained in the device node.
31 Each port node contains an 'endpoint' subnode for each remote device port
32 connected to this port. If a single port is connected to more than one
34 If more than one port is present in a device node or there is more than one
35 endpoint at a port, or a port node needs to be associated with a selected
44 port@0 {
59 port@1 {
66 All 'port' nodes can be grouped under an optional 'ports' node, which
67 allows to specify #address-cells, #size-cells properties for the 'port'
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | thine,thc63lvd1024.yaml | 34 single-link mode, all pixels are received on port@0, and port@1 shall not
36 received on port@0 and odd-numbered pixels on port@1, and both port@0 and
37 port@1 shall contain endpoints.
46 port@0:
48 description: First LVDS input port
50 port@1:
52 description: Second LVDS input port
54 port@2:
58 port@3:
63 - port@0
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.txt | 4 time. Active port input stream will be de-serialized and its content outputted
5 through PARALLEL output port.
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
9 PARALLEL output port has a maximum width of 12 bits.
25 - ports: A ports node with one port child node per device input and output
26 port, in accordance with the video interface bindings defined in
28 port nodes are numbered as follows:
30 Port Description
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| D | adv7180.yaml | 38 port:
47 A node containing input and output port nodes with endpoint definitions
73 - port
88 port@3:
90 description: Output port
93 "^port@[0-2]$":
95 description: Input port
98 - port@3
118 port@6:
120 description: Output port
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| D | tvp5150.txt | 17 The device node must contain one 'port' child node per device physical input
18 and output port, in accordance with the video interface bindings defined in
19 Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
22 Name Type Port
28 The device node must contain at least one sink port and the src port. Each input
29 port must be linked to an endpoint defined in [1]. The port/connector layout is
32 tvp-5150 port@0 (AIP1A)
33 endpoint@0 -----------> Comp0-Con port
34 endpoint@1 ------+----> Svideo-Con port
35 tvp-5150 port@1 (AIP1B) |
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| /Documentation/firmware-guide/acpi/dsd/ |
| D | graph.rst | 38 The port and endpoint concepts are very similar to those in Devicetree
39 [3]. A port represents an interface in a device, and an endpoint
42 All port nodes are located under the device's "_DSD" node in the hierarchical
43 data extension tree. The data extension related to each port node must begin
44 with "port" and must be followed by the "@" character and the number of the
45 port as its key. The target object it refers to should be called "PRTX", where
46 "X" is the number of the port. An example of such a package would be::
48 Package() { "port@4", "PRT4" }
50 Further on, endpoints are located under the port nodes. The hierarchical
54 number of the port and "Y" is the number of the endpoint. An example of such a
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| /Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 15 - portN-mode: String specifying the port mode for port N, where N can be
16 from 1 to 3. If the port mode is not specified, that port is treated
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
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| /Documentation/devicetree/bindings/usb/ |
| D | ti,hd3ss3220.yaml | 7 title: TI HD3SS3220 TypeC DRP Port Controller
13 HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel
15 HD3SS3220 can be configured as a Downstream Facing Port (DFP), Upstream Facing Port (UFP) or a
16 Dual Role Port (DRP) making it ideal for any application.
33 port@0:
36 $ref: /connector/usb-connector.yaml#/properties/ports/properties/port@1
38 port@1:
43 - port@0
44 - port@1
68 port@0 {
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,j721e-dss.yaml | 38 - description: VP1 video port 1
39 - description: VP2 video port 2
40 - description: VP3 video port 3
41 - description: VP4 video port 4
67 - description: vp1 Video Port 1 pixel clock
68 - description: vp2 Video Port 2 pixel clock
69 - description: vp3 Video Port 3 pixel clock
70 - description: vp4 Video Port 4 pixel clock
109 port@0:
112 The output port node form video port 1
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| /Documentation/networking/ |
| D | switchdev.rst | 52 | | v offloaded data path | mgmt port
86 port, called the port netdev. A port netdev is the software representation of
87 the physical port and provides a conduit for control traffic to/from the
90 standard netdev tools (iproute2, ethtool, etc), the port netdev can also
91 provide to the user access to the physical properties of the switch port such
95 port netdevs. All of the switchdev driver ops are netdev ops or switchdev ops.
97 A switch management port is outside the scope of the switchdev driver model.
98 Typically, the management port is not participating in offloaded data plane and
99 is loaded with a different driver, such as a NIC driver, on the management port
106 ndo_get_port_parent_id for each port netdev, returning the same physical ID for
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| /Documentation/devicetree/bindings/media/ |
| D | video-mux.txt | 5 on the active input port is passed through to the output port. Muxes described
14 - port@*: at least three port nodes containing endpoints connecting to the
15 source and sink devices according to of_graph bindings. The last port is
16 the output port, all others are inputs.
18 Optionally, #address-cells, #size-cells, and port nodes can be grouped under a
36 port@0 {
44 port@1 {
52 port@2 {
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| /Documentation/devicetree/bindings/sound/ |
| D | eukrea-tlv320.txt | 11 - fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX).
13 - fsl,mux-ext-port : The external port of the i.MX audio muxer.
15 Note: The AUDMUX port numbering should start at 1, which is consistent with
24 fsl,mux-int-port = <2>;
25 fsl,mux-ext-port = <3>;
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