| /arch/sh/lib/ |
| D | checksum.S | 48 mov r4, r0
49 tst #3, r0 ! Check alignment.
53 tst #1, r0 ! Check alignment.
60 mov.b @r4+, r0
61 extu.b r0, r0
62 addc r0, r6 ! t=0 from previous tst
63 mov r6, r0
65 shlr16 r0
66 shlr8 r0
67 or r0, r6
[all …]
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| D | ashrsi3.S | 30 ! r0: Result
41 ! r0: Shifts
45 ! r0: Result
56 mov r5,r0
59 and #31,r0
61 mov r0,r4
62 mova ashrsi3_table,r0
63 mov.b @(r0,r4),r4
64 add r4,r0
65 jmp @r0
[all …]
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| D | ashlsi3.S | 30 ! r0: Result
41 ! r0: Shifts
45 ! r0: Result
57 mov r5,r0
60 and #31,r0
62 mov r0,r4
63 mova ashlsi3_table,r0
64 mov.b @(r0,r4),r4
65 add r4,r0
66 jmp @r0
[all …]
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| D | lshrsi3.S | 30 ! r0: Result
40 ! r0: Value to shift
45 ! r0: Result
56 mov r5,r0
59 and #31,r0
61 mov r0,r4
62 mova lshrsi3_table,r0
63 mov.b @(r0,r4),r4
64 add r4,r0
65 jmp @r0
[all …]
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| D | udivsi3_i4i.S | 44 mov r4,r0
45 shlr8 r0
51 shlr r0
55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
63 mova div_table_ix,r0
65 mov.b @(r0,r5),r1
68 mova div_table_ix,r0
[all …]
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| D | copy_page.S | 34 mov #(PAGE_SIZE >> 10), r0
35 shll8 r0
36 shll2 r0
37 add r0,r8
39 1: mov.l @r11+,r0
48 movca.l r0,@r10
50 mov.l r0,@r10
86 mov #11,r0
88 cmp/gt r0,r6 ! r6 (len) > r0 (11)
94 neg r5,r0
[all …]
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| /arch/arm/lib/ |
| D | delay-loop.S | 25 mul r0, r2, r0 @ r0 = delay_us * UDELAY_MULT
26 ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0xfffffaf0
29 umull r1, r0, r2, r0 @ r0-r1 = r0 * loops_per_jiffy
31 adcs r0, r0, r0 @ and right shift by 31
38 subs r0, r0, #1
41 subs r0, r0, #1
43 subs r0, r0, #1
45 subs r0, r0, #1
47 subs r0, r0, #1
49 subs r0, r0, #1
[all …]
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| D | getuser.S | 33 check_uaccess r0, 1, r1, r2, __get_user_bad
34 1: TUSER(ldrb) r2, [r0]
35 mov r0, #0
41 check_uaccess r0, 2, r1, r2, __get_user_bad
44 2: TUSER(ldrh) r2, [r0]
50 2: ldrbt r2, [r0], #1
51 3: ldrbt rb, [r0], #0
53 rb .req r0
54 2: ldrb r2, [r0]
55 3: ldrb rb, [r0, #1]
[all …]
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| /arch/arm/mm/ |
| D | proc-arm946.S | 43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 bic r0, r0, #0x00001000 @ i-cache
45 bic r0, r0, #0x00000004 @ d-cache
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 ret r0
73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
82 mov r0, #0
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
131 sub r3, r1, r0 @ calculate total size
137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| D | cache-v6.S | 36 mov r0, #0
40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
62 mov r0, #0
64 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
[all …]
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| D | cache-fa.S | 44 mov r0, #0
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
86 sub r3, r1, r0 @ calculate total size
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
92 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
93 add r0, r0, #CACHE_DLINESIZE
94 cmp r0, r1
126 bic r0, r0, #CACHE_DLINESIZE - 1
127 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
128 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
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| D | proc-arm740.S | 37 mrc p15, 0, r0, c1, c0, 0
38 bic r0, r0, #0x3f000000 @ bank/f/lock/s
39 bic r0, r0, #0x0000000c @ w-buffer/cache
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 ret r0
61 mov r0, #0
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
64 mcr p15, 0, r0, c6, c3 @ disable area 3~7
65 mcr p15, 0, r0, c6, c4
66 mcr p15, 0, r0, c6, c5
[all …]
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| D | proc-arm925.S | 81 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
82 bic r0, r0, #0x1000 @ ...i............
83 bic r0, r0, #0x000e @ ............wca.
84 mcr p15, 0, r0, c1, c0, 0 @ disable caches
118 ret r0
127 mov r0, #0
129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
142 mov r0, #0
143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-arm926.S | 50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
51 bic r0, r0, #0x1000 @ ...i............
52 bic r0, r0, #0x000e @ ............wca.
53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 ret r0
89 mov r0, #0
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
108 mov r0, #0
109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-mohawk.S | 41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 bic r0, r0, #0x1800 @ ...iz...........
43 bic r0, r0, #0x0006 @ .............ca.
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 ret r0
80 mov r0, #0
81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
91 mov r0, #0
92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| /arch/arm/mach-pxa/ |
| D | standby.S | 22 ldr r0, =PSSR
31 str r1, [r0] @ make sure PSSR_PH/STS are clear
64 mcr p14, 0, r0, c7, c0, 0
69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
70 bic r0, r0, #PXA3_DDR_HCAL_HCEN
71 str r0, [r1, #PXA3_DDR_HCAL]
72 1: ldr r0, [r1, #PXA3_DDR_HCAL]
73 tst r0, #PXA3_DDR_HCAL_HCEN
76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
77 orr r0, r0, #PXA3_RCOMP_SWEVAL
[all …]
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| /arch/powerpc/lib/ |
| D | checksum_64.S | 24 addic r0,r5,0 /* clear carry */
46 adde r0,r0,r6
81 adde r0,r0,r6
85 adde r0,r0,r9
90 adde r0,r0,r10
92 adde r0,r0,r11
94 adde r0,r0,r12
96 adde r0,r0,r14
98 adde r0,r0,r15
102 adde r0,r0,r16
[all …]
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| D | checksum_32.S | 30 andi. r0,r3,2 /* Align buffer to longword boundary */
32 lhz r0,4(r3) /* do 2 bytes to get aligned */
36 adde r5,r5,r0
41 2: lwzu r0,4(r3)
42 adde r5,r5,r0
46 lwz r0,4(r3)
49 adde r5,r5,r0
55 22: lwz r0,4(r3)
58 adde r5,r5,r0
65 3: andi. r0,r4,2
[all …]
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| /arch/sh/kernel/cpu/shmobile/ |
| D | sleep.S | 21 #define k0 r0
34 stc vbr, r0
35 mov.l r0, @(SH_SLEEP_VBR, r5)
41 sts pr, r0
42 mov.l r0, @(SH_SLEEP_SPC, r5)
45 stc sr, r0
46 mov.l r0, @(SH_SLEEP_SR, r5)
49 mov.l @(SH_SLEEP_MODE, r5), r0
50 tst #SUSP_SH_REGS, r0
93 mov #SH_SLEEP_REG_STBCR, r0
[all …]
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| /arch/arm/mach-exynos/ |
| D | sleep.S | 36 mrc p15, 0, r0, c0, c0, 0
38 and r0, r0, r1
40 cmp r0, r1
50 mrc p15, 0, r0, c0, c0, 0
52 and r0, r0, r1
54 cmp r0, r1
57 adr r0, _cp15_save_power
58 ldr r1, [r0]
59 ldr r1, [r0, r1]
60 adr r0, _cp15_save_diag
[all …]
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| /arch/arc/lib/ |
| D | strcmp.S | 16 or r2,r0,r1
22 ld.ab r2,[r0,4]
31 xor r0,r2,r3 ; mask for difference
32 sub_s r1,r0,1
33 bic_s r0,r0,r1 ; mask for least significant difference bit
34 sub r1,r5,r0
35 xor r0,r5,r1 ; mask for least significant difference byte
36 and_s r2,r2,r0
37 and_s r3,r3,r0
40 mov_s r0,1
[all …]
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| /arch/powerpc/kernel/ |
| D | cpu_setup_ppc970.S | 16 mfmsr r0
17 rldicl. r0,r0,4,63
24 li r0,0
26 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
27 rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
33 rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
40 mfspr r0,SPRN_HID1
43 or r0,r0,r3
44 mtspr SPRN_HID1,r0
45 mtspr SPRN_HID1,r0
[all …]
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| /arch/arm/mach-omap2/ |
| D | sleep44xx.S | 63 cmp r0, #0x0
71 ldr r9, [r0, #OMAP_TYPE_OFFSET]
74 mov r0, #SCU_PM_NORMAL
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
104 mov r8, r0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
109 ands r0, r0, #0x0f
110 ldreq r0, [r8, #SCU_OFFSET0]
[all …]
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| /arch/arm/mach-tegra/ |
| D | sleep-tegra30.S | 135 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
189 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
205 ldr r0, [r2]
236 mov r4, r0
238 mov r0, #TEGRA_FLUSH_CACHE_ALL
240 mov r0, r4
256 add r3, r3, r0
258 mov32 r0, tegra30_tear_down_core
260 sub r0, r0, r1
262 add r0, r0, r1
[all …]
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| /arch/microblaze/kernel/ |
| D | head.S | 66 mts rmsr, r0
68 mts rslr, r0
69 addi r8, r0, 0xFFFFFFFF
90 lbui r11, r0, TOPHYS(endian_check)
92 lw r11, r0, r7 /* Big endian load in delay slot */
93 lwr r11, r0, r7 /* Little endian load */
97 or r7, r0, r0 /* clear R7 when not valid DTB */
100 or r11, r0, r0 /* incremment */
101 ori r4, r0, TOPHYS(_fdt_start)
102 ori r3, r0, (0x10000 - 4)
[all …]
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