| /drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_ctl.c | 83 void ctl_write(struct mdp5_ctl *ctl, u32 reg, u32 data) in ctl_write() argument
85 struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm); in ctl_write()
87 (void)ctl->reg_offset; /* TODO use this instead of mdp5_write */ in ctl_write()
92 u32 ctl_read(struct mdp5_ctl *ctl, u32 reg) in ctl_read() argument
94 struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm); in ctl_read()
96 (void)ctl->reg_offset; /* TODO use this instead of mdp5_write */ in ctl_read()
135 static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in set_ctl_op() argument
163 spin_lock_irqsave(&ctl->hw_lock, flags); in set_ctl_op()
164 ctl_write(ctl, REG_MDP5_CTL_OP(ctl->id), ctl_op); in set_ctl_op()
165 spin_unlock_irqrestore(&ctl->hw_lock, flags); in set_ctl_op()
[all …]
|
| D | mdp5_ctl.h | 29 int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
33 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *p);
34 int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *p,
37 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
55 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
72 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
74 u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
|
| D | mdp5_encoder.c | 135 struct mdp5_ctl *ctl = mdp5_encoder->ctl; in mdp5_vid_encoder_disable() local
145 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_vid_encoder_disable()
150 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_disable()
169 struct mdp5_ctl *ctl = mdp5_encoder->ctl; in mdp5_vid_encoder_enable() local
181 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_enable()
183 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_vid_encoder_enable()
234 struct mdp5_ctl *ctl = mdp5_encoder->ctl; in mdp5_encoder_atomic_check() local
236 mdp5_cstate->ctl = ctl; in mdp5_encoder_atomic_check()
312 mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true); in mdp5_vid_encoder_set_split_display()
339 struct mdp5_ctl *ctl) in mdp5_encoder_init() argument
[all …]
|
| /drivers/thunderbolt/ |
| D | ctl.c | 53 #define tb_ctl_WARN(ctl, format, arg...) \ argument
54 dev_WARN(&(ctl)->nhi->pdev->dev, format, ## arg)
56 #define tb_ctl_err(ctl, format, arg...) \ argument
57 dev_err(&(ctl)->nhi->pdev->dev, format, ## arg)
59 #define tb_ctl_warn(ctl, format, arg...) \ argument
60 dev_warn(&(ctl)->nhi->pdev->dev, format, ## arg)
62 #define tb_ctl_info(ctl, format, arg...) \ argument
63 dev_info(&(ctl)->nhi->pdev->dev, format, ## arg)
65 #define tb_ctl_dbg(ctl, format, arg...) \ argument
66 dev_dbg(&(ctl)->nhi->pdev->dev, format, ## arg)
[all …]
|
| D | ctl.h | 26 void tb_ctl_start(struct tb_ctl *ctl);
27 void tb_ctl_stop(struct tb_ctl *ctl);
28 void tb_ctl_free(struct tb_ctl *ctl);
47 struct tb_ctl *ctl; member
78 struct tb_ctl *ctl; member
103 int tb_cfg_request(struct tb_ctl *ctl, struct tb_cfg_request *req,
106 struct tb_cfg_result tb_cfg_request_sync(struct tb_ctl *ctl,
125 int tb_cfg_ack_plug(struct tb_ctl *ctl, u64 route, u32 port, bool unplug);
126 struct tb_cfg_result tb_cfg_reset(struct tb_ctl *ctl, u64 route);
127 struct tb_cfg_result tb_cfg_read_raw(struct tb_ctl *ctl, void *buffer,
[all …]
|
| D | eeprom.c | 18 static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) in tb_eeprom_ctl_write() argument
20 return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); in tb_eeprom_ctl_write()
26 static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) in tb_eeprom_ctl_read() argument
28 return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); in tb_eeprom_ctl_read()
44 struct tb_eeprom_ctl ctl; in tb_eeprom_active() local
45 int res = tb_eeprom_ctl_read(sw, &ctl); in tb_eeprom_active()
49 ctl.access_high = 1; in tb_eeprom_active()
50 res = tb_eeprom_ctl_write(sw, &ctl); in tb_eeprom_active()
53 ctl.access_low = 0; in tb_eeprom_active()
54 return tb_eeprom_ctl_write(sw, &ctl); in tb_eeprom_active()
[all …]
|
| /drivers/hwmon/ |
| D | axi-fan-control.c | 63 const struct axi_fan_control_data *ctl) in axi_iowrite() argument
65 iowrite32(val, ctl->base + reg); in axi_iowrite()
69 const struct axi_fan_control_data *ctl) in axi_ioread() argument
71 return ioread32(ctl->base + reg); in axi_ioread()
80 struct axi_fan_control_data *ctl = dev_get_drvdata(dev); in axi_fan_control_show() local
82 u32 temp = axi_ioread(attr->index, ctl); in axi_fan_control_show()
92 struct axi_fan_control_data *ctl = dev_get_drvdata(dev); in axi_fan_control_store() local
102 axi_iowrite(temp, attr->index, ctl); in axi_fan_control_store()
107 static long axi_fan_control_get_pwm_duty(const struct axi_fan_control_data *ctl) in axi_fan_control_get_pwm_duty() argument
109 u32 pwm_width = axi_ioread(ADI_REG_PWM_WIDTH, ctl); in axi_fan_control_get_pwm_duty()
[all …]
|
| /drivers/irqchip/ |
| D | irq-meson-gpio.c | 48 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
50 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl);
51 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
54 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
57 void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
59 void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
146 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl, in meson_gpio_irq_update_bits() argument
152 spin_lock_irqsave(&ctl->lock, flags); in meson_gpio_irq_update_bits()
154 tmp = readl_relaxed(ctl->base + reg); in meson_gpio_irq_update_bits()
157 writel_relaxed(tmp, ctl->base + reg); in meson_gpio_irq_update_bits()
[all …]
|
| /drivers/misc/ |
| D | vmw_balloon.c | 662 struct vmballoon_ctl *ctl, in vmballoon_alloc_page_list() argument
674 if (!list_empty(&ctl->prealloc_pages)) { in vmballoon_alloc_page_list()
675 page = list_first_entry(&ctl->prealloc_pages, in vmballoon_alloc_page_list()
679 if (ctl->page_size == VMW_BALLOON_2M_PAGE) in vmballoon_alloc_page_list()
686 ctl->page_size); in vmballoon_alloc_page_list()
691 list_add(&page->lru, &ctl->pages); in vmballoon_alloc_page_list()
697 ctl->page_size); in vmballoon_alloc_page_list()
701 ctl->n_pages = i; in vmballoon_alloc_page_list()
703 return req_n_pages == ctl->n_pages ? 0 : -ENOMEM; in vmballoon_alloc_page_list()
855 static int vmballoon_lock(struct vmballoon *b, struct vmballoon_ctl *ctl) in vmballoon_lock() argument
[all …]
|
| /drivers/crypto/caam/ |
| D | debugfs.c | 40 debugfs_create_file("qi_congested", 0444, ctrlpriv->ctl, in caam_debugfs_qi_init()
56 ctrlpriv->ctl = debugfs_create_dir("ctl", root); in caam_debugfs_init()
58 debugfs_create_file("rq_dequeued", 0444, ctrlpriv->ctl, in caam_debugfs_init()
60 debugfs_create_file("ob_rq_encrypted", 0444, ctrlpriv->ctl, in caam_debugfs_init()
62 debugfs_create_file("ib_rq_decrypted", 0444, ctrlpriv->ctl, in caam_debugfs_init()
64 debugfs_create_file("ob_bytes_encrypted", 0444, ctrlpriv->ctl, in caam_debugfs_init()
66 debugfs_create_file("ob_bytes_protected", 0444, ctrlpriv->ctl, in caam_debugfs_init()
68 debugfs_create_file("ib_bytes_decrypted", 0444, ctrlpriv->ctl, in caam_debugfs_init()
70 debugfs_create_file("ib_bytes_validated", 0444, ctrlpriv->ctl, in caam_debugfs_init()
74 debugfs_create_file("fault_addr", 0444, ctrlpriv->ctl, in caam_debugfs_init()
[all …]
|
| /drivers/misc/habanalabs/include/gaudi/ |
| D | gaudi_packets.h | 62 __le32 ctl; member
67 __le32 ctl; member
72 __le32 ctl; member
77 __le32 ctl; member
86 __le32 ctl; member
119 __le32 ctl; member
124 __le32 ctl; member
142 __le32 ctl; member
159 __le32 ctl; member
166 __le32 ctl; member
[all …]
|
| /drivers/net/ethernet/chelsio/cxgb/ |
| D | mv88e1xxx.c | 50 u32 ctl; in mv88e1xxx_reset() local
56 (void) simple_mdio_read(cphy, MII_BMCR, &ctl); in mv88e1xxx_reset()
57 ctl &= BMCR_RESET; in mv88e1xxx_reset()
58 if (ctl) in mv88e1xxx_reset()
60 } while (ctl && --time_out); in mv88e1xxx_reset()
62 return ctl ? -1 : 0; in mv88e1xxx_reset()
127 u32 ctl; in mv88e1xxx_set_speed_duplex() local
129 (void) simple_mdio_read(phy, MII_BMCR, &ctl); in mv88e1xxx_set_speed_duplex()
131 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); in mv88e1xxx_set_speed_duplex()
133 ctl |= BMCR_SPEED100; in mv88e1xxx_set_speed_duplex()
[all …]
|
| /drivers/mmc/host/ |
| D | sdhci-milbeaut.c | 89 u32 ctl; in sdhci_milbeaut_reset() local
118 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
119 ctl |= F_SDH30_CMD_DAT_DELAY; in sdhci_milbeaut_reset()
120 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
179 u32 ctl; in sdhci_milbeaut_vendor_init() local
181 ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
182 ctl |= F_SDH30_CRES_O_DN; in sdhci_milbeaut_vendor_init()
183 sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
184 ctl &= ~F_SDH30_MSEL_O_1_8; in sdhci_milbeaut_vendor_init()
185 sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
[all …]
|
| D | tmio_mmc.h | 134 void __iomem *ctl; member
232 return ioread16(host->ctl + (addr << host->bus_shift)); in sd_ctrl_read16()
238 ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count); in sd_ctrl_read16_rep()
244 return ioread16(host->ctl + (addr << host->bus_shift)) | in sd_ctrl_read16_and_16_as_32()
245 ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16; in sd_ctrl_read16_and_16_as_32()
251 ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count); in sd_ctrl_read32_rep()
262 iowrite16(val, host->ctl + (addr << host->bus_shift)); in sd_ctrl_write16()
268 iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count); in sd_ctrl_write16_rep()
277 iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift)); in sd_ctrl_write32_as_16_and_16()
278 iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); in sd_ctrl_write32_as_16_and_16()
[all …]
|
| /drivers/net/wireless/broadcom/b43/ |
| D | pio.c | 318 u16 ctl, in tx_write_2byte_queue() argument
326 ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI; in tx_write_2byte_queue()
327 b43_piotx_write16(q, B43_PIO_TXCTL, ctl); in tx_write_2byte_queue()
337 ctl &= ~B43_PIO_TXCTL_WRITEHI; in tx_write_2byte_queue()
338 b43_piotx_write16(q, B43_PIO_TXCTL, ctl); in tx_write_2byte_queue()
346 return ctl; in tx_write_2byte_queue()
355 u16 ctl; in pio_tx_frame_2byte_queue() local
357 ctl = b43_piotx_read16(q, B43_PIO_TXCTL); in pio_tx_frame_2byte_queue()
358 ctl |= B43_PIO_TXCTL_FREADY; in pio_tx_frame_2byte_queue()
359 ctl &= ~B43_PIO_TXCTL_EOF; in pio_tx_frame_2byte_queue()
[all …]
|
| /drivers/misc/habanalabs/include/goya/ |
| D | goya_packets.h | 70 __le32 ctl; member
75 __le32 ctl; member
83 __le32 ctl; member
88 __le32 ctl; member
94 __le32 ctl; member
100 __le32 ctl; member
105 __le32 ctl; member
111 __le32 ctl; member
131 __le32 ctl; member
138 __le32 ctl; member
|
| /drivers/clk/ingenic/ |
| D | cgu.c | 88 u32 ctl; in ingenic_pll_recalc_rate() local
93 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
95 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); in ingenic_pll_recalc_rate()
97 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); in ingenic_pll_recalc_rate()
99 od_enc = ctl >> pll_info->od_shift; in ingenic_pll_recalc_rate()
103 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_recalc_rate()
105 bypass = !!(ctl & BIT(pll_info->bypass_bit)); in ingenic_pll_recalc_rate()
183 u32 ctl; in ingenic_pll_check_stable() local
185 return readl_poll_timeout(cgu->base + pll_info->reg, ctl, in ingenic_pll_check_stable()
186 ctl & BIT(pll_info->stable_bit), in ingenic_pll_check_stable()
[all …]
|
| /drivers/net/ |
| D | sungem_phy.c | 316 u16 ctl, adv; in genmii_setup_aneg() local
338 ctl = sungem_phy_read(phy, MII_BMCR); in genmii_setup_aneg()
339 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); in genmii_setup_aneg()
340 sungem_phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
347 u16 ctl; in genmii_setup_forced() local
354 ctl = sungem_phy_read(phy, MII_BMCR); in genmii_setup_forced()
355 ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_ANENABLE); in genmii_setup_forced()
358 sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
365 ctl |= BMCR_SPEED100; in genmii_setup_forced()
372 ctl |= BMCR_FULLDPLX; in genmii_setup_forced()
[all …]
|
| /drivers/ntb/hw/mscc/ |
| D | ntb_hw_switchtec.c | 99 struct ntb_ctrl_regs __iomem *ctl, in switchtec_ntb_part_op() argument
126 iowrite32(op, &ctl->partition_op); in switchtec_ntb_part_op()
130 iowrite32(NTB_CTRL_PART_OP_RESET, &ctl->partition_op); in switchtec_ntb_part_op()
134 ps = ioread32(&ctl->partition_status) & 0xFFFF; in switchtec_ntb_part_op()
147 ioread32(&ctl->partition_status)); in switchtec_ntb_part_op()
223 struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_peer_ctrl; in switchtec_ntb_mw_clr_direct() local
227 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_clr_direct()
229 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_clr_direct()
230 iowrite32(0, &ctl->bar_entry[bar].win_size); in switchtec_ntb_mw_clr_direct()
231 iowrite32(0, &ctl->bar_ext_entry[bar].win_size); in switchtec_ntb_mw_clr_direct()
[all …]
|
| /drivers/hwtracing/intel_th/ |
| D | pti.c | 152 u32 ctl = PTI_EN; in intel_th_pti_activate() local
155 ctl |= pti->patgen << __ffs(PTI_PATGENMODE); in intel_th_pti_activate()
157 ctl |= PTI_FCEN; in intel_th_pti_activate()
158 ctl |= pti->mode << __ffs(PTI_MODE); in intel_th_pti_activate()
159 ctl |= pti->clkdiv << __ffs(PTI_CLKDIV); in intel_th_pti_activate()
160 ctl |= pti->lpp_dest << __ffs(LPP_DEST); in intel_th_pti_activate()
162 iowrite32(ctl, pti->base + REG_PTI_CTL); in intel_th_pti_activate()
180 u32 ctl = ioread32(pti->base + REG_PTI_CTL); in read_hw_config() local
182 pti->mode = (ctl & PTI_MODE) >> __ffs(PTI_MODE); in read_hw_config()
183 pti->clkdiv = (ctl & PTI_CLKDIV) >> __ffs(PTI_CLKDIV); in read_hw_config()
[all …]
|
| /drivers/char/hw_random/ |
| D | octeon-rng.c | 30 union cvmx_rnm_ctl_status ctl; in octeon_rng_init() local
33 ctl.u64 = 0; in octeon_rng_init()
34 ctl.s.ent_en = 1; /* Enable the entropy source. */ in octeon_rng_init()
35 ctl.s.rng_en = 1; /* Enable the RNG hardware. */ in octeon_rng_init()
36 cvmx_write_csr((__force u64)p->control_status, ctl.u64); in octeon_rng_init()
42 union cvmx_rnm_ctl_status ctl; in octeon_rng_cleanup() local
45 ctl.u64 = 0; in octeon_rng_cleanup()
47 cvmx_write_csr((__force u64)p->control_status, ctl.u64); in octeon_rng_cleanup()
|
| /drivers/net/wireless/ath/wcn36xx/ |
| D | dxe.c | 59 struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl, *next; in wcn36xx_dxe_free_ctl_block() local
62 for (i = 0; i < ch->desc_num && ctl; i++) { in wcn36xx_dxe_free_ctl_block()
63 next = ctl->next; in wcn36xx_dxe_free_ctl_block()
64 kfree(ctl); in wcn36xx_dxe_free_ctl_block()
65 ctl = next; in wcn36xx_dxe_free_ctl_block()
291 struct wcn36xx_dxe_ctl *ctl, in wcn36xx_dxe_fill_skb() argument
294 struct wcn36xx_dxe_desc *dxe = ctl->desc; in wcn36xx_dxe_fill_skb()
310 ctl->skb = skb; in wcn36xx_dxe_fill_skb()
401 struct wcn36xx_dxe_ctl *ctl; in reap_tx_dxes() local
411 ctl = ch->tail_blk_ctl; in reap_tx_dxes()
[all …]
|
| /drivers/tty/serial/ |
| D | owl-uart.c | 96 u32 ctl; in owl_uart_set_mctrl() local
98 ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_set_mctrl()
101 ctl |= OWL_UART_CTL_LBEN; in owl_uart_set_mctrl()
103 ctl &= ~OWL_UART_CTL_LBEN; in owl_uart_set_mctrl()
105 owl_uart_write(port, ctl, OWL_UART_CTL); in owl_uart_set_mctrl()
111 u32 stat, ctl; in owl_uart_get_mctrl() local
113 ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_get_mctrl()
117 if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE)) in owl_uart_get_mctrl()
335 u32 ctl; in owl_uart_set_termios() local
340 ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_set_termios()
[all …]
|
| /drivers/net/ethernet/ibm/emac/ |
| D | phy.c | 112 int ctl, adv; in genmii_setup_aneg() local
120 ctl = phy_read(phy, MII_BMCR); in genmii_setup_aneg()
121 if (ctl < 0) in genmii_setup_aneg()
122 return ctl; in genmii_setup_aneg()
123 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); in genmii_setup_aneg()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
162 ctl = phy_read(phy, MII_BMCR); in genmii_setup_aneg()
163 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
171 int ctl; in genmii_setup_forced() local
[all …]
|
| /drivers/net/ethernet/micrel/ |
| D | ks8842.c | 422 struct ks8842_tx_dma_ctl *ctl = &adapter->dma_tx; in ks8842_tx_frame_dma() local
423 u8 *buf = ctl->buf; in ks8842_tx_frame_dma()
425 if (ctl->adesc) { in ks8842_tx_frame_dma()
431 sg_dma_len(&ctl->sg) = skb->len + sizeof(u32); in ks8842_tx_frame_dma()
442 sg_dma_address(&ctl->sg), 0, sg_dma_len(&ctl->sg), in ks8842_tx_frame_dma()
446 if (sg_dma_len(&ctl->sg) % 4) in ks8842_tx_frame_dma()
447 sg_dma_len(&ctl->sg) += 4 - sg_dma_len(&ctl->sg) % 4; in ks8842_tx_frame_dma()
449 ctl->adesc = dmaengine_prep_slave_sg(ctl->chan, in ks8842_tx_frame_dma()
450 &ctl->sg, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); in ks8842_tx_frame_dma()
451 if (!ctl->adesc) in ks8842_tx_frame_dma()
[all …]
|