| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.h | 32 struct dc;
34 void dcn10_hw_sequencer_construct(struct dc *dc);
38 struct dc *dc,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
46 struct dc *dc);
48 struct dc *dc,
51 struct dc *dc,
54 struct dc *dc,
57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
59 struct dc *dc,
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| D | dcn10_hw_sequencer.c | 84 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
93 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
101 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
115 dc->hwss.pipe_control_lock(dc, pipe_ctx, true); in dcn10_lock_all_pipes()
117 dc->hwss.pipe_control_lock(dc, pipe_ctx, false); in dcn10_lock_all_pipes()
121 static void log_mpc_crc(struct dc *dc, in log_mpc_crc() argument
124 struct dc_context *dc_ctx = dc->ctx; in log_mpc_crc()
125 struct dce_hwseq *hws = dc->hwseq; in log_mpc_crc()
135 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx) in dcn10_log_hubbub_state() argument
137 struct dc_context *dc_ctx = dc->ctx; in dcn10_log_hubbub_state()
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| /drivers/dma/ |
| D | txx9dmac.c | 24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
39 #define channel64_readl(dc, name) \ argument
40 __raw_readl(&(__dma_regs(dc)->name))
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer.h | 48 void (*hardware_release)(struct dc *dc);
55 void (*init_hw)(struct dc *dc);
56 void (*power_down_on_boot)(struct dc *dc);
57 void (*enable_accelerated_mode)(struct dc *dc,
59 enum dc_status (*apply_ctx_to_hw)(struct dc *dc,
61 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
62 void (*apply_ctx_for_surface)(struct dc *dc,
65 void (*program_front_end_for_ctx)(struct dc *dc,
67 void (*wait_for_pending_cleared)(struct dc *dc,
69 void (*post_unlock_program_front_end)(struct dc *dc,
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| D | hw_sequencer_private.h | 72 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
73 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
74 void (*init_pipes)(struct dc *dc, struct dc_state *context);
75 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
76 void (*update_plane_addr)(const struct dc *dc,
78 void (*plane_atomic_disconnect)(struct dc *dc,
80 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
81 bool (*set_input_transfer_func)(struct dc *dc,
84 bool (*set_output_transfer_func)(struct dc *dc,
87 void (*power_down)(struct dc *dc);
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| /drivers/tty/ |
| D | nozomi.c | 331 struct nozomi *dc; member
479 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
481 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
488 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
489 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
490 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
491 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
492 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
493 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
494 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.h | 36 struct dc *dc,
39 struct dc *dc,
41 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
42 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
43 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
45 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 void dcn20_program_output_csc(struct dc *dc,
55 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
57 struct dc *dc,
61 struct dc *dc,
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| D | dcn20_resource.h | 34 struct dc;
43 struct dc *dc);
53 struct dc *dc,
69 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
102 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
117 struct dc *dc,
121 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
123 struct dc *dc,
126 struct dc *dc,
134 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
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| D | dcn20_hwseq.c | 67 static int find_free_gsl_group(const struct dc *dc) in find_free_gsl_group() argument
69 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
71 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
73 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
95 const struct dc *dc, in dcn20_setup_gsl_group_as_lock() argument
111 group_idx = find_free_gsl_group(dc); in dcn20_setup_gsl_group_as_lock()
119 dc->res_pool->gsl_groups.gsl_0 = 1; in dcn20_setup_gsl_group_as_lock()
123 dc->res_pool->gsl_groups.gsl_1 = 1; in dcn20_setup_gsl_group_as_lock()
127 dc->res_pool->gsl_groups.gsl_2 = 1; in dcn20_setup_gsl_group_as_lock()
145 dc->res_pool->gsl_groups.gsl_0 = 0; in dcn20_setup_gsl_group_as_lock()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 80 dc->ctx
83 dc->ctx->logger
146 static void destroy_links(struct dc *dc) in destroy_links() argument
150 for (i = 0; i < dc->link_count; i++) { in destroy_links()
151 if (NULL != dc->links[i]) in destroy_links()
152 link_destroy(&dc->links[i]); in destroy_links()
183 struct dc *dc, in create_links() argument
188 struct dc_bios *bios = dc->ctx->dc_bios; in create_links()
190 dc->link_count = 0; in create_links()
214 …ct table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count); in create_links()
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| D | dc_stream.c | 37 #define DC_LOGGER dc->ctx->logger
50 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
245 struct dc *dc = stream->ctx->dc; in dc_stream_get_status() local
246 return dc_stream_get_status_from_state(dc->current_state, stream); in dc_stream_get_status()
250 struct dc *dc, in program_cursor_attributes() argument
261 res_ctx = &dc->current_state->res_ctx; in program_cursor_attributes()
271 dc->hwss.cursor_lock(dc, pipe_to_program, true); in program_cursor_attributes()
274 dc->hwss.set_cursor_attribute(pipe_ctx); in program_cursor_attributes()
275 if (dc->hwss.set_cursor_sdr_white_level) in program_cursor_attributes()
276 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in program_cursor_attributes()
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| /drivers/md/bcache/ |
| D | writeback.c | 30 static uint64_t __calc_target_rate(struct cached_dev *dc) in __calc_target_rate() argument
32 struct cache_set *c = dc->disk.c; in __calc_target_rate()
48 div64_u64(bdev_sectors(dc->bdev) << WRITEBACK_SHARE_SHIFT, in __calc_target_rate()
52 div_u64(cache_sectors * dc->writeback_percent, 100); in __calc_target_rate()
61 static void __update_writeback_rate(struct cached_dev *dc) in __update_writeback_rate() argument
83 int64_t target = __calc_target_rate(dc); in __update_writeback_rate()
84 int64_t dirty = bcache_dev_sectors_dirty(&dc->disk); in __update_writeback_rate()
87 div_s64(error, dc->writeback_rate_p_term_inverse); in __update_writeback_rate()
101 struct cache_set *c = dc->disk.c; in __update_writeback_rate()
105 if (dc->writeback_consider_fragment && in __update_writeback_rate()
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| /drivers/md/ |
| D | dm-delay.c | 53 struct delay_c *dc = from_timer(dc, t, delay_timer); in handle_delayed_timer() local
55 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
58 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
60 mutex_lock(&dc->timer_lock); in queue_timeout()
62 if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires) in queue_timeout()
63 mod_timer(&dc->delay_timer, expires); in queue_timeout()
65 mutex_unlock(&dc->timer_lock); in queue_timeout()
80 static struct bio *flush_delayed_bios(struct delay_c *dc, int flush_all) in flush_delayed_bios() argument
88 list_for_each_entry_safe(delayed, next, &dc->delayed_bios, list) { in flush_delayed_bios()
107 queue_timeout(dc, next_expires); in flush_delayed_bios()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 59 dc->ctx->logger
66 void dcn31_init_hw(struct dc *dc) in dcn31_init_hw() argument
68 struct abm **abms = dc->res_pool->multiple_abms; in dcn31_init_hw()
69 struct dce_hwseq *hws = dc->hwseq; in dcn31_init_hw()
70 struct dc_bios *dcb = dc->ctx->dc_bios; in dcn31_init_hw()
71 struct resource_pool *res_pool = dc->res_pool; in dcn31_init_hw()
76 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) in dcn31_init_hw()
77 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); in dcn31_init_hw()
79 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn31_init_hw()
85 if (!dc->debug.disable_clock_gate) { in dcn31_init_hw()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_stream.h | 304 bool dc_update_planes_and_stream(struct dc *dc,
319 void dc_commit_updates_for_stream(struct dc *dc,
328 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
330 uint8_t dc_get_current_stream_count(struct dc *dc);
331 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
357 struct dc *dc,
362 struct dc *dc,
368 const struct dc *dc,
374 const struct dc *dc,
380 const struct dc *dc,
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| D | dc.h | 285 struct dc;
291 bool (*get_dcc_compression_cap)(const struct dc *dc,
423 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
424 dm_get_timestamp(dc->ctx) : 0
427 if (dc->debug.bw_val_profile.enable) \
428 dc->debug.bw_val_profile.total_count++
431 if (dc->debug.bw_val_profile.enable) { \
433 voltage_level_tick = dm_get_timestamp(dc->ctx); \
434 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
438 if (dc->debug.bw_val_profile.enable) \
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 40 dc->ctx->logger
318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
453 const struct dc *dc, in dcn_bw_calc_rq_dlg_ttu() argument
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu()
494 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
503 dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep; in dcn_bw_calc_rq_dlg_ttu()
636 static bool dcn_bw_apply_registry_override(struct dc *dc) in dcn_bw_apply_registry_override() argument
641 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns in dcn_bw_apply_registry_override()
642 && dc->debug.sr_exit_time_ns) { in dcn_bw_apply_registry_override()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 64 dc->ctx->logger
97 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
144 bool dcn30_set_input_transfer_func(struct dc *dc, in dcn30_set_input_transfer_func() argument
148 struct dce_hwseq *hws = dc->hwseq; in dcn30_set_input_transfer_func()
187 bool dcn30_set_output_transfer_func(struct dc *dc, in dcn30_set_output_transfer_func() argument
192 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
220 struct dc *dc, in dcn30_set_writeback() argument
230 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
231 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
235 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
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| D | dcn30_hwseq.h | 31 struct dc;
33 void dcn30_init_hw(struct dc *dc);
35 struct dc *dc,
39 struct dc *dc,
43 struct dc *dc,
47 struct dc *dc,
51 struct dc *dc,
58 bool dcn30_set_input_transfer_func(struct dc *dc,
61 bool dcn30_set_output_transfer_func(struct dc *dc,
68 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane,
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| D | dcn30_resource.h | 34 struct dc;
43 struct dc *dc);
46 struct dc *dc,
56 bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
59 struct dc *dc,
66 struct dc *dc, struct dc_state *context,
70 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
72 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
75 struct dc *dc, struct dc_state *context,
93 struct dc *dc,
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| /drivers/scsi/esas2r/ |
| D | esas2r_disc.c | 291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
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| /drivers/gpu/drm/tegra/ |
| D | dc.c | 44 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
48 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
49 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
50 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
73 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
81 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
87 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
90 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
92 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
115 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
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| D | rgb.c | 18 struct tegra_dc *dc; member
78 static void tegra_dc_write_regs(struct tegra_dc *dc, in tegra_dc_write_regs() argument
85 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
93 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); in tegra_rgb_encoder_disable()
94 tegra_dc_commit(rgb->dc); in tegra_rgb_encoder_disable()
103 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); in tegra_rgb_encoder_enable()
106 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
109 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
112 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
117 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); in tegra_rgb_encoder_enable()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | Makefile | 57 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
60 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
61 CFLAGS_$(AMDDALPATH)/dc/dml/dcn2x/dcn2x.o := $(dml_ccflags)
62 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
63 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
64 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
65 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags)
66 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
67 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
68 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
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| /drivers/clk/mvebu/ |
| D | dove-divider.c | 51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
74 if (dc->divider_table) { in dove_calc_divider()
77 for (i = 0; dc->divider_table[i]; i++) in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
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