| /drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource.h | 173 #define ABM_DCN32_REG_LIST_RI(id) \ argument
190 #define AUD_COMMON_REG_LIST_RI(id) \ argument
204 #define VPG_DCN3_REG_LIST_RI(id) \ argument
214 #define AFMT_DCN3_REG_LIST_RI(id) \ argument
226 #define APG_DCN31_REG_LIST_RI(id) \ argument
233 #define SE_DCN32_REG_LIST_RI(id) \ argument
283 #define AUX_REG_LIST_RI(id) \ argument
289 #define DCN2_AUX_REG_LIST_RI(id) \ argument
295 #define HPD_REG_LIST_RI(id) SRI_ARR(DC_HPD_CONTROL, HPD, id) argument
298 #define LE_DCN3_REG_LIST_RI(id) \ argument
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| D | dcn32_resource.c | 118 #define SR_ARR(reg_name, id) \ argument
121 #define SR_ARR_INIT(reg_name, id, value) \ argument
124 #define SRI(reg_name, block, id)\ argument
128 #define SRI_ARR(reg_name, block, id)\ argument
132 #define SR_ARR_I2C(reg_name, id) \ argument
135 #define SRI_ARR_I2C(reg_name, block, id)\ argument
139 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
143 #define SRI2(reg_name, block, id)\ argument
146 #define SRI2_ARR(reg_name, block, id)\ argument
150 #define SRIR(var_name, reg_name, block, id)\ argument
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| /drivers/media/platform/samsung/s3c-camif/ |
| D | camif-regs.h | 65 #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id)) argument
71 #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) argument
73 #define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4) argument
75 #define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4) argument
78 #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) argument
98 #define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs))) argument
111 #define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs))) argument
114 #define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs))) argument
117 #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) argument
147 #define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs))) argument
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| /drivers/reset/ |
| D | reset-uniphier.c | 16 unsigned int id; member
158 #define UNIPHIER_MIO_RESET_SD(id, ch) \ argument
161 #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \ argument
164 #define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \ argument
167 #define UNIPHIER_MIO_RESET_USB2(id, ch) \ argument
170 #define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \ argument
173 #define UNIPHIER_MIO_RESET_DMAC(id) \ argument
202 #define UNIPHIER_PERI_RESET_UART(id, ch) \ argument
205 #define UNIPHIER_PERI_RESET_I2C(id, ch) \ argument
208 #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ argument
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| /drivers/gpu/drm/amd/display/dc/dcn321/ |
| D | dcn321_resource.c | 121 #define SR_ARR(reg_name, id)\ argument
124 #define SR_ARR_INIT(reg_name, id, value)\ argument
127 #define SRI(reg_name, block, id)\ argument
131 #define SRI_ARR(reg_name, block, id)\ argument
135 #define SR_ARR_I2C(reg_name, id) \ argument
138 #define SRI_ARR_I2C(reg_name, block, id)\ argument
142 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
146 #define SRI2(reg_name, block, id)\ argument
149 #define SRI2_ARR(reg_name, block, id)\ argument
153 #define SRIR(var_name, reg_name, block, id)\ argument
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| /drivers/gpu/host1x/hw/ |
| D | hw_host1x02_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| D | hw_host1x04_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| D | hw_host1x01_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| D | hw_host1x05_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r()
60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ argument
62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ argument
116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) in host1x_sync_mlock_owner_r()
120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ argument
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_manager.c | 35 #define IS_MASTER_DSI_LINK(id) (msm_dsim_glb.master_dsi_link_id == id) argument
63 static inline struct msm_dsi *dsi_mgr_get_dsi(int id) in dsi_mgr_get_dsi()
68 static inline struct msm_dsi *dsi_mgr_get_other_dsi(int id) in dsi_mgr_get_other_dsi()
73 static int dsi_mgr_parse_of(struct device_node *np, int id) in dsi_mgr_parse_of()
94 static int dsi_mgr_setup_components(int id) in dsi_mgr_setup_components()
152 dsi_mgr_phy_enable(int id, in dsi_mgr_phy_enable()
193 static void dsi_mgr_phy_disable(int id) in dsi_mgr_phy_disable()
216 int id; member
227 static void msm_dsi_manager_set_split_display(u8 id) in msm_dsi_manager_set_split_display()
259 int id = dsi_mgr_bridge_get_id(bridge); in dsi_mgr_bridge_power_on() local
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 120 #define SRI(reg_name, block, id)\ argument
124 #define SRI2(reg_name, block, id)\ argument
128 #define SRIR(var_name, reg_name, block, id)\ argument
132 #define SRII(reg_name, block, id)\ argument
136 #define SRII2(reg_name_pre, reg_name_post, id)\ argument
141 #define SRII_MPC_RMU(reg_name, block, id)\ argument
145 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
149 #define DCCG_SRII(reg_name, block, id)\ argument
153 #define VUPDATE_SRII(reg_name, block, id)\ argument
215 #define abm_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn316/ |
| D | dcn316_resource.c | 155 #define SRI(reg_name, block, id)\ argument
159 #define SRI2(reg_name, block, id)\ argument
163 #define SRIR(var_name, reg_name, block, id)\ argument
167 #define SRII(reg_name, block, id)\ argument
171 #define SRII_MPC_RMU(reg_name, block, id)\ argument
175 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
179 #define DCCG_SRII(reg_name, block, id)\ argument
183 #define VUPDATE_SRII(reg_name, block, id)\ argument
224 #define abm_regs(id)\ argument
244 #define audio_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 197 #define SRI(reg_name, block, id)\ argument
200 #define SRI2(reg_name, block, id)\ argument
203 #define SRII(reg_name, block, id)\ argument
207 #define DCCG_SRII(reg_name, block, id)\ argument
211 #define VUPDATE_SRII(reg_name, block, id)\ argument
215 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
219 #define SRII_MPC_RMU(reg_name, block, id)\ argument
235 #define vmid_regs(id)\ argument
289 #define vpg_regs(id)\ argument
321 #define afmt_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 176 #define SRI(reg_name, block, id)\ argument
179 #define SRI2(reg_name, block, id)\ argument
182 #define SRII(reg_name, block, id)\ argument
186 #define DCCG_SRII(reg_name, block, id)\ argument
190 #define VUPDATE_SRII(reg_name, block, id)\ argument
194 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
198 #define SRII_MPC_RMU(reg_name, block, id)\ argument
214 #define vmid_regs(id)\ argument
268 #define vpg_regs(id)\ argument
297 #define afmt_regs(id)\ argument
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| /drivers/net/ethernet/intel/fm10k/ |
| D | fm10k_tlv.h | 62 unsigned int id; member
67 #define FM10K_TLV_ATTR_NULL_STRING(id, len) { id, FM10K_TLV_NULL_STRING, len } argument
68 #define FM10K_TLV_ATTR_MAC_ADDR(id) { id, FM10K_TLV_MAC_ADDR, 6 } argument
69 #define FM10K_TLV_ATTR_BOOL(id) { id, FM10K_TLV_BOOL, 0 } argument
70 #define FM10K_TLV_ATTR_U8(id) { id, FM10K_TLV_UNSIGNED, 1 } argument
71 #define FM10K_TLV_ATTR_U16(id) { id, FM10K_TLV_UNSIGNED, 2 } argument
72 #define FM10K_TLV_ATTR_U32(id) { id, FM10K_TLV_UNSIGNED, 4 } argument
73 #define FM10K_TLV_ATTR_U64(id) { id, FM10K_TLV_UNSIGNED, 8 } argument
74 #define FM10K_TLV_ATTR_S8(id) { id, FM10K_TLV_SIGNED, 1 } argument
75 #define FM10K_TLV_ATTR_S16(id) { id, FM10K_TLV_SIGNED, 2 } argument
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| /drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_resource.c | 163 #define SRI(reg_name, block, id)\ argument
167 #define SRI2(reg_name, block, id)\ argument
171 #define SRIR(var_name, reg_name, block, id)\ argument
175 #define SRII(reg_name, block, id)\ argument
179 #define SRII_MPC_RMU(reg_name, block, id)\ argument
183 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
187 #define DCCG_SRII(reg_name, block, id)\ argument
191 #define VUPDATE_SRII(reg_name, block, id)\ argument
255 #define abm_regs(id)\ argument
275 #define audio_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 132 #define SRI(reg_name, block, id)\ argument
136 #define SRI2(reg_name, block, id)\ argument
140 #define SRIR(var_name, reg_name, block, id)\ argument
144 #define SRII(reg_name, block, id)\ argument
148 #define SRII_MPC_RMU(reg_name, block, id)\ argument
152 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
156 #define DCCG_SRII(reg_name, block, id)\ argument
160 #define VUPDATE_SRII(reg_name, block, id)\ argument
232 #define abm_regs(id)\ argument
252 #define audio_regs(id)\ argument
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| /drivers/gpu/drm/amd/display/dc/gpio/ |
| D | gpio_service.c | 131 enum gpio_id id; in dal_gpio_service_create_irq() local
147 enum gpio_id id; in dal_gpio_service_create_generic_mux() local
178 enum gpio_id id, in dal_gpio_get_generic_pin_info()
239 enum gpio_id id, in is_pin_busy()
247 enum gpio_id id, in set_pin_busy()
255 enum gpio_id id, in set_pin_free()
263 enum gpio_id id, in dal_gpio_service_lock()
277 enum gpio_id id, in dal_gpio_service_unlock()
293 enum gpio_id id = gpio->id; in dal_gpio_service_open() local
377 enum gpio_id id = dal_gpio_get_id(irq); in dal_irq_get_source() local
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| /drivers/gpu/drm/amd/display/dc/dcn315/ |
| D | dcn315_resource.c | 167 #define SRI(reg_name, block, id)\ argument
171 #define SRI2(reg_name, block, id)\ argument
175 #define SRIR(var_name, reg_name, block, id)\ argument
179 #define SRII(reg_name, block, id)\ argument
183 #define SRII_MPC_RMU(reg_name, block, id)\ argument
187 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
191 #define DCCG_SRII(reg_name, block, id)\ argument
195 #define VUPDATE_SRII(reg_name, block, id)\ argument
236 #define abm_regs(id)\ argument
256 #define audio_regs(id)\ argument
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| /drivers/macintosh/ |
| D | adbhid.c | 212 int id; member
268 int id = (data[0] >> 4) & 0x0f; in adbhid_keyboard_input() local
285 adbhid_input_keycode(int id, int scancode, int repeat) in adbhid_input_keycode()
407 int id = (data[0] >> 4) & 0x0f; in adbhid_mouse_input() local
505 int id = (data[0] >> 4) & 0x0f; in adbhid_buttons_input() local
753 adbhid_input_register(int id, int default_id, int original_handler_id, in adbhid_input_register()
914 static void adbhid_input_unregister(int id) in adbhid_input_unregister()
924 adbhid_input_reregister(int id, int default_id, int org_handler_id, in adbhid_input_reregister()
961 int id = keyboard_ids.id[i]; in adbhid_probe() local
985 int id = buttons_ids.id[i]; in adbhid_probe() local
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| /drivers/i2c/busses/ |
| D | i2c-cadence.c | 233 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) in cdns_i2c_clear_bus_hold()
240 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) in cdns_is_holdquirk()
247 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) in cdns_i2c_set_mode()
290 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) in cdns_i2c_slave_rcv_data()
311 static void cdns_i2c_slave_send_data(struct cdns_i2c *id) in cdns_i2c_slave_send_data()
338 struct cdns_i2c *id = ptr; in cdns_i2c_slave_isr() local
399 struct cdns_i2c *id = ptr; in cdns_i2c_master_isr() local
552 struct cdns_i2c *id = ptr; in cdns_i2c_isr() local
564 static void cdns_i2c_mrecv(struct cdns_i2c *id) in cdns_i2c_mrecv()
662 static void cdns_i2c_msend(struct cdns_i2c *id) in cdns_i2c_msend()
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_resource.c | 255 #define SRI(reg_name, block, id)\ argument
259 #define SRIR(var_name, reg_name, block, id)\ argument
263 #define SRII(reg_name, block, id)\ argument
267 #define SRI_IX(reg_name, block, id)\ argument
270 #define DCCG_SRII(reg_name, block, id)\ argument
274 #define VUPDATE_SRII(reg_name, block, id)\ argument
323 #define audio_regs(id)\ argument
346 #define stream_enc_regs(id)\ argument
372 #define aux_regs(id)\ argument
382 #define hpd_regs(id)\ argument
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| /drivers/clk/mediatek/ |
| D | reset.c | 21 unsigned long id, bool deassert) in mtk_reset_update()
32 unsigned long id) in mtk_reset_assert()
38 unsigned long id) in mtk_reset_deassert()
43 static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id) in mtk_reset()
55 unsigned long id, bool deassert) in mtk_reset_update_set_clr()
67 unsigned long id) in mtk_reset_assert_set_clr()
73 unsigned long id) in mtk_reset_deassert_set_clr()
79 unsigned long id) in mtk_reset_set_clr()
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| /drivers/gpu/drm/amd/display/dc/bios/dce112/ |
| D | command_table_helper_dce112.c | 95 enum clock_source_id id) in clock_source_id_to_atom_phy_clk_src_id()
120 static uint8_t hpd_sel_to_atom(enum hpd_source_id id) in hpd_sel_to_atom()
151 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) in dig_encoder_sel_to_atom()
162 enum clock_source_id id, in clock_source_id_to_atom()
212 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id) in engine_bp_to_atom()
306 enum bp_dce_clock_type id, in dc_clock_type_to_atom()
330 static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id) in transmitter_color_depth_to_atom()
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| D | command_table_helper2_dce112.c | 95 enum clock_source_id id) in clock_source_id_to_atom_phy_clk_src_id()
120 static uint8_t hpd_sel_to_atom(enum hpd_source_id id) in hpd_sel_to_atom()
151 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) in dig_encoder_sel_to_atom()
162 enum clock_source_id id, in clock_source_id_to_atom()
212 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id) in engine_bp_to_atom()
306 enum bp_dce_clock_type id, in dc_clock_type_to_atom()
330 static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id) in transmitter_color_depth_to_atom()
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