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Searched refs:pwr_reg (Results 1 – 25 of 27) sorted by relevance

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/drivers/mmc/host/
Dmmci_stm32_sdmmc.c354 pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN | in mmci_sdmmc_set_pwrreg()
529 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN); in sdmmc_pre_sig_volt_vswitch()
541 host->pwr_reg & MCI_STM32_VSWITCHEN) { in sdmmc_post_sig_volt_switch()
542 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH); in sdmmc_post_sig_volt_switch()
554 mmci_write_pwrreg(host, host->pwr_reg & in sdmmc_post_sig_volt_switch()
584 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER); in sdmmc_variant_init()
Dmmci.h407 u32 pwr_reg; member
Dmmci.c381 if (host->pwr_reg != pwr) { in mmci_write_pwrreg()
382 host->pwr_reg = pwr; in mmci_write_pwrreg()
1686 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_irq_thread()
2331 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_restore()
/drivers/pinctrl/renesas/
Dpinctrl-rzg2l.c556 u32 pwr_reg = 0x0; in rzg2l_pinctrl_pinconf_get() local
559 pwr_reg = SD_CH(0); in rzg2l_pinctrl_pinconf_get()
561 pwr_reg = SD_CH(1); in rzg2l_pinctrl_pinconf_get()
563 pwr_reg = QSPI; in rzg2l_pinctrl_pinconf_get()
568 addr = pctrl->base + pwr_reg; in rzg2l_pinctrl_pinconf_get()
653 u32 pwr_reg = 0x0; in rzg2l_pinctrl_pinconf_set() local
659 pwr_reg = SD_CH(0); in rzg2l_pinctrl_pinconf_set()
661 pwr_reg = SD_CH(1); in rzg2l_pinctrl_pinconf_set()
663 pwr_reg = QSPI; in rzg2l_pinctrl_pinconf_set()
667 addr = pctrl->base + pwr_reg; in rzg2l_pinctrl_pinconf_set()
/drivers/usb/gadget/udc/
Ds3c2410_udc.c119 u32 addr_reg, pwr_reg, ep_int_reg, usb_int_reg; in s3c2410_udc_debugfs_show() local
125 pwr_reg = udc_read(S3C2410_UDC_PWR_REG); in s3c2410_udc_debugfs_show()
158 addr_reg, pwr_reg, ep_int_reg, usb_int_reg, in s3c2410_udc_debugfs_show()
841 int pwr_reg; in s3c2410_udc_irq() local
864 pwr_reg = udc_read(S3C2410_UDC_PWR_REG); in s3c2410_udc_irq()
870 usb_status, usbd_status, pwr_reg, ep0csr); in s3c2410_udc_irq()
885 ep0csr, pwr_reg); in s3c2410_udc_irq()
960 if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) { in s3c2410_udc_irq()
/drivers/clk/mediatek/
Dclk-pll.h28 u32 pwr_reg; member
Dclk-mt8195-apusys_pll.c32 .pwr_reg = _pwr_reg, \
Dclk-mt7986-apmixed.c29 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
Dclk-mt8186-apmixedsys.c24 .pwr_reg = _pwr_reg, \
Dclk-mt8195-apmixedsys.c39 .pwr_reg = _pwr_reg, \
Dclk-mt6795-apmixedsys.c29 .pwr_reg = _pwr_reg, \
Dclk-mt8135.c603 .pwr_reg = _pwr_reg, \
Dclk-mt7629.c31 .pwr_reg = _pwr_reg, \
Dclk-mt7622.c31 .pwr_reg = _pwr_reg, \
Dclk-mt6797.c606 .pwr_reg = _pwr_reg, \
Dclk-mt8516.c707 .pwr_reg = _pwr_reg, \
Dclk-pll.c326 pll->pwr_addr = base + data->pwr_reg; in mtk_clk_register_pll()
Dclk-mt6765.c675 .pwr_reg = _pwr_reg, \
Dclk-mt2701.c928 .pwr_reg = _pwr_reg, \
Dclk-mt8167.c989 .pwr_reg = _pwr_reg, \
Dclk-mt6779.c1154 .pwr_reg = _pwr_reg, \
Dclk-mt8183.c1073 .pwr_reg = _pwr_reg, \
Dclk-mt2712.c1138 .pwr_reg = _pwr_reg, \
Dclk-mt8365.c771 .pwr_reg = _pwr_reg, \
/drivers/gpu/drm/msm/hdmi/
Dhdmi.c410 HDMI_CFG(pwr_reg, 8x74),

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