| /arch/alpha/lib/ |
| D | fpreg.c | 14 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
16 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
22 unsigned long val; in alpha_read_fp_reg() local
28 val = current_thread_info()->fp[reg]; in alpha_read_fp_reg()
30 case 0: STT( 0, val); break; in alpha_read_fp_reg()
31 case 1: STT( 1, val); break; in alpha_read_fp_reg()
32 case 2: STT( 2, val); break; in alpha_read_fp_reg()
33 case 3: STT( 3, val); break; in alpha_read_fp_reg()
34 case 4: STT( 4, val); break; in alpha_read_fp_reg()
35 case 5: STT( 5, val); break; in alpha_read_fp_reg()
[all …]
|
| /arch/arm/include/asm/hardware/ |
| D | cp14.h | 12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
[all …]
|
| /arch/mips/pci/ |
| D | pci-bcm63xx.c | 109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); in bcm63xx_int_cfg_writel()
123 u32 val; in bcm63xx_reset_pcie() local
132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie()
133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; in bcm63xx_reset_pcie()
134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie()
152 u32 val; in bcm63xx_register_pcie() local
164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); in bcm63xx_register_pcie()
165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie()
166 val |= OPT1_RD_REPLY_BE_FIX_EN; in bcm63xx_register_pcie()
[all …]
|
| /arch/loongarch/include/asm/ |
| D | percpu.h | 41 unsigned long val, int size) \
50 : [val] "r" (val)); \
56 : [val] "r" (val)); \
63 return ret c_op val; \
108 static __always_inline void __percpu_write(void *ptr, unsigned long val, int size) in __percpu_write() argument
114 : [val] "r" (val), [ptr] "r" (ptr) in __percpu_write()
120 : [val] "r" (val), [ptr] "r" (ptr) in __percpu_write()
126 : [val] "r" (val), [ptr] "r" (ptr) in __percpu_write()
132 : [val] "r" (val), [ptr] "r" (ptr) in __percpu_write()
140 static __always_inline unsigned long __percpu_xchg(void *ptr, unsigned long val, in __percpu_xchg() argument
[all …]
|
| /arch/mips/include/asm/ |
| D | mipsregs.h | 1383 #define write_r10k_perf_cntr(counter,val) \ argument
1388 : "r" (val), "i" (counter)); \
1402 #define write_r10k_perf_cntl(counter,val) \ argument
1407 : "r" (val), "i" (counter)); \
1509 #define __write_ulong_c0_register(reg, sel, val) \ argument
1512 __write_32bit_c0_register(reg, sel, val); \
1514 __write_64bit_c0_register(reg, sel, val); \
1568 #define __write_64bit_c0_split(source, sel, val) \ argument
1570 unsigned long long __tmp = (val); \
1655 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) argument
[all …]
|
| D | mipsmtregs.h | 20 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val) argument
26 #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val) argument
29 #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) argument
32 #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) argument
35 #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) argument
39 #define write_c0_tchalt(val) __write_32bit_c0_register($2, 4, val) argument
42 #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) argument
375 #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) argument
377 #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) argument
379 #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) argument
[all …]
|
| /arch/arm64/boot/dts/ti/ |
| D | k3-pinctrl.h | 41 #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
42 #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
44 #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
45 #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
47 #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
48 #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
50 #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
51 #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
53 #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
54 #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
[all …]
|
| /arch/s390/include/asm/ |
| D | percpu.h | 27 #define arch_this_cpu_to_op_simple(pcp, val, op) \ argument
37 new__ = old__ op (val); \
44 #define this_cpu_add_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
45 #define this_cpu_add_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
46 #define this_cpu_add_return_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
47 #define this_cpu_add_return_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
48 #define this_cpu_and_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
49 #define this_cpu_and_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
50 #define this_cpu_or_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
51 #define this_cpu_or_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
[all …]
|
| /arch/powerpc/lib/ |
| D | qspinlock.c | 104 static inline int decode_tail_cpu(u32 val) in decode_tail_cpu() argument
106 return (val >> _Q_TAIL_CPU_OFFSET) - 1; in decode_tail_cpu()
109 static inline int get_owner_cpu(u32 val) in get_owner_cpu() argument
111 return (val & _Q_OWNER_CPU_MASK) >> _Q_OWNER_CPU_OFFSET; in get_owner_cpu()
144 : "r" (&lock->val), "r"(tail), "r" (newval), in trylock_clean_tail()
174 : "r" (&lock->val), "r" (tail), "r"(_Q_TAIL_CPU_MASK) in publish_tail_cpu()
190 : "r" (&lock->val), "r" (_Q_MUST_Q_VAL) in set_mustq()
206 : "r" (&lock->val), "r" (_Q_MUST_Q_VAL) in clear_mustq()
228 : "r" (&lock->val), "r"(old), "r" (new) in try_set_sleepy()
234 static __always_inline void seen_sleepy_owner(struct qspinlock *lock, u32 val) in seen_sleepy_owner() argument
[all …]
|
| /arch/alpha/include/uapi/asm/ |
| D | compiler.h | 14 # define __kernel_insbl(val, shift) __builtin_alpha_insbl(val, shift) argument
15 # define __kernel_inswl(val, shift) __builtin_alpha_inswl(val, shift) argument
16 # define __kernel_insql(val, shift) __builtin_alpha_insql(val, shift) argument
17 # define __kernel_inslh(val, shift) __builtin_alpha_inslh(val, shift) argument
18 # define __kernel_extbl(val, shift) __builtin_alpha_extbl(val, shift) argument
19 # define __kernel_extwl(val, shift) __builtin_alpha_extwl(val, shift) argument
22 # define __kernel_insbl(val, shift) \ argument
24 __asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
26 # define __kernel_inswl(val, shift) \ argument
28 __asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
[all …]
|
| /arch/mips/bcm63xx/ |
| D | cs.c | 38 u32 val; in bcm63xx_set_cs_base() local
50 val = (base & MPI_CSBASE_BASE_MASK); in bcm63xx_set_cs_base()
52 val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT; in bcm63xx_set_cs_base()
55 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); in bcm63xx_set_cs_base()
70 u32 val; in bcm63xx_set_cs_timing() local
76 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
77 val &= ~(MPI_CSCTL_WAIT_MASK); in bcm63xx_set_cs_timing()
78 val &= ~(MPI_CSCTL_SETUP_MASK); in bcm63xx_set_cs_timing()
79 val &= ~(MPI_CSCTL_HOLD_MASK); in bcm63xx_set_cs_timing()
80 val |= wait << MPI_CSCTL_WAIT_SHIFT; in bcm63xx_set_cs_timing()
[all …]
|
| /arch/x86/include/asm/ |
| D | percpu.h | 76 #define __pcpu_cast_1(val) ((u8)(((unsigned long) val) & 0xff)) argument
77 #define __pcpu_cast_2(val) ((u16)(((unsigned long) val) & 0xffff)) argument
78 #define __pcpu_cast_4(val) ((u32)(((unsigned long) val) & 0xffffffff)) argument
79 #define __pcpu_cast_8(val) ((u64)(val)) argument
111 : [val] __pcpu_reg_imm_##size(pto_val__)); \
124 #define percpu_add_op(size, qual, var, val) \ argument
126 const int pao_ID__ = (__builtin_constant_p(val) && \
127 ((val) == 1 || (val) == -1)) ? \
128 (int)(val) : 0; \
131 pao_tmp__ = (val); \
[all …]
|
| D | special_insns.h | 24 void native_write_cr0(unsigned long val);
28 unsigned long val; in native_read_cr0() local
29 asm volatile("mov %%cr0,%0\n\t" : "=r" (val) : __FORCE_ORDER); in native_read_cr0()
30 return val; in native_read_cr0()
35 unsigned long val; in native_read_cr2() local
36 asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : __FORCE_ORDER); in native_read_cr2()
37 return val; in native_read_cr2()
40 static __always_inline void native_write_cr2(unsigned long val) in native_write_cr2() argument
42 asm volatile("mov %0,%%cr2": : "r" (val) : "memory"); in native_write_cr2()
47 unsigned long val; in __native_read_cr3() local
[all …]
|
| /arch/arm64/include/asm/ |
| D | percpu.h | 61 static inline void __percpu_write_##sz(void *ptr, unsigned long val) \
63 WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \
68 __percpu_##name##_case_##sz(void *ptr, unsigned long val) \
84 : [val] "r" ((u##sz)(val))); \
89 __percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \
106 : [val] "r" ((u##sz)(val))); \
174 #define this_cpu_write_1(pcp, val) \ argument
175 _pcp_protect(__percpu_write_8, pcp, (unsigned long)val)
176 #define this_cpu_write_2(pcp, val) \ argument
177 _pcp_protect(__percpu_write_16, pcp, (unsigned long)val)
[all …]
|
| D | arm_pmuv3.h | 23 write_sysreg(val, pmevcntr##n##_el0)
24 static inline void write_pmevcntrn(int n, unsigned long val) in write_pmevcntrn() argument
30 write_sysreg(val, pmevtyper##n##_el0)
31 static inline void write_pmevtypern(int n, unsigned long val) in write_pmevtypern() argument
49 static inline void write_pmcr(u64 val) in write_pmcr() argument
51 write_sysreg(val, pmcr_el0); in write_pmcr()
59 static inline void write_pmselr(u32 val) in write_pmselr() argument
61 write_sysreg(val, pmselr_el0); in write_pmselr()
64 static inline void write_pmccntr(u64 val) in write_pmccntr() argument
66 write_sysreg(val, pmccntr_el0); in write_pmccntr()
[all …]
|
| /arch/powerpc/platforms/powernv/ |
| D | vas-window.c | 276 u64 lpcr, val; in init_xlate_regs() local
282 val = 0ULL; in init_xlate_regs()
283 val = SET_FIELD(VAS_XLATE_MSR_HV, val, 1); in init_xlate_regs()
284 val = SET_FIELD(VAS_XLATE_MSR_SF, val, 1); in init_xlate_regs()
286 val = SET_FIELD(VAS_XLATE_MSR_DR, val, 1); in init_xlate_regs()
287 val = SET_FIELD(VAS_XLATE_MSR_PR, val, 1); in init_xlate_regs()
289 write_hvwc_reg(window, VREG(XLATE_MSR), val); in init_xlate_regs()
292 val = 0ULL; in init_xlate_regs()
300 val = SET_FIELD(VAS_XLATE_LPCR_PAGE_SIZE, val, 5); in init_xlate_regs()
301 val = SET_FIELD(VAS_XLATE_LPCR_ISL, val, lpcr & LPCR_ISL); in init_xlate_regs()
[all …]
|
| /arch/x86/kernel/ |
| D | quirks.c | 75 u32 val; in ich_force_hpet_resume() local
83 val = readl(rcba_base + 0x3404); in ich_force_hpet_resume()
84 if (!(val & 0x80)) { in ich_force_hpet_resume()
86 writel(val | 0x80, rcba_base + 0x3404); in ich_force_hpet_resume()
89 val = readl(rcba_base + 0x3404); in ich_force_hpet_resume()
90 if (!(val & 0x80)) in ich_force_hpet_resume()
98 u32 val; in ich_force_enable_hpet() local
122 val = readl(rcba_base + 0x3404); in ich_force_enable_hpet()
124 if (val & 0x80) { in ich_force_enable_hpet()
126 val = val & 0x3; in ich_force_enable_hpet()
[all …]
|
| /arch/sparc/kernel/ |
| D | pcr.c | 57 u64 val; in direct_pcr_read() local
60 __asm__ __volatile__("rd %%pcr, %0" : "=r" (val)); in direct_pcr_read()
61 return val; in direct_pcr_read()
64 static void direct_pcr_write(unsigned long reg_num, u64 val) in direct_pcr_write() argument
67 __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (val)); in direct_pcr_write()
72 u64 val; in direct_pic_read() local
75 __asm__ __volatile__("rd %%pic, %0" : "=r" (val)); in direct_pic_read()
76 return val; in direct_pic_read()
79 static void direct_pic_write(unsigned long reg_num, u64 val) in direct_pic_write() argument
91 "rd %%pic, %%g0" : : "r" (val)); in direct_pic_write()
[all …]
|
| /arch/arc/include/asm/ |
| D | spinlock.h | 19 unsigned int val; in arch_spin_lock() local
27 : [val] "=&r" (val) in arch_spin_lock()
46 unsigned int val, got_it = 0; in arch_spin_trylock() local
56 : [val] "=&r" (val), in arch_spin_trylock()
81 unsigned int val; in arch_read_lock() local
100 : [val] "=&r" (val) in arch_read_lock()
111 unsigned int val, got_it = 0; in arch_read_trylock() local
123 : [val] "=&r" (val), in arch_read_trylock()
136 unsigned int val; in arch_write_lock() local
157 : [val] "=&r" (val) in arch_write_lock()
[all …]
|
| /arch/arm64/kvm/hyp/ |
| D | vgic-v3-sr.c | 61 static void __gic_v3_set_lr(u64 val, int lr) in __gic_v3_set_lr() argument
65 write_gicreg(val, ICH_LR0_EL2); in __gic_v3_set_lr()
68 write_gicreg(val, ICH_LR1_EL2); in __gic_v3_set_lr()
71 write_gicreg(val, ICH_LR2_EL2); in __gic_v3_set_lr()
74 write_gicreg(val, ICH_LR3_EL2); in __gic_v3_set_lr()
77 write_gicreg(val, ICH_LR4_EL2); in __gic_v3_set_lr()
80 write_gicreg(val, ICH_LR5_EL2); in __gic_v3_set_lr()
83 write_gicreg(val, ICH_LR6_EL2); in __gic_v3_set_lr()
86 write_gicreg(val, ICH_LR7_EL2); in __gic_v3_set_lr()
89 write_gicreg(val, ICH_LR8_EL2); in __gic_v3_set_lr()
[all …]
|
| /arch/arm/mach-hisi/ |
| D | hotplug.c | 77 u32 val = 0; in set_cpu_hi3620() local
90 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN in set_cpu_hi3620()
92 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
94 val |= CPU0_HPM_SRST_REQ_EN; in set_cpu_hi3620()
95 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); in set_cpu_hi3620()
104 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
105 val &= ~(CPU0_WFI_MASK_CFG << cpu); in set_cpu_hi3620()
106 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
109 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN in set_cpu_hi3620()
111 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
[all …]
|
| /arch/powerpc/platforms/cell/ |
| D | pmu.c | 43 #define READ_SHADOW_REG(val, reg) \ argument
47 (val) = shadow_regs->reg; \
50 #define READ_MMIO_UPPER32(val, reg) \ argument
54 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
64 u32 val_in_latch, val = 0; in cbe_read_phys_ctr() local
71 READ_SHADOW_REG(val, pm_ctr[phys_ctr]); in cbe_read_phys_ctr()
73 READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]); in cbe_read_phys_ctr()
77 return val; in cbe_read_phys_ctr()
81 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val) in cbe_write_phys_ctr() argument
91 WRITE_WO_MMIO(pm_ctr[phys_ctr], val); in cbe_write_phys_ctr()
[all …]
|
| /arch/arm/include/asm/ |
| D | cp15.h | 59 unsigned long val; in get_cr() local
60 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); in get_cr()
61 return val; in get_cr()
64 static inline void set_cr(unsigned long val) in set_cr() argument
67 : : "r" (val) : "cc"); in set_cr()
73 unsigned int val; in get_auxcr() local
74 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val)); in get_auxcr()
75 return val; in get_auxcr()
78 static inline void set_auxcr(unsigned int val) in set_auxcr() argument
81 : : "r" (val)); in set_auxcr()
[all …]
|
| /arch/arm64/kvm/ |
| D | vgic-sys-reg-v3.c | 14 u64 val) in set_gic_ctlr() argument
26 host_pri_bits = FIELD_GET(ICC_CTLR_EL1_PRI_BITS_MASK, val) + 1; in set_gic_ctlr()
32 host_id_bits = FIELD_GET(ICC_CTLR_EL1_ID_BITS_MASK, val); in set_gic_ctlr()
39 seis = FIELD_GET(ICC_CTLR_EL1_SEIS_MASK, val); in set_gic_ctlr()
44 a3v = FIELD_GET(ICC_CTLR_EL1_A3V_MASK, val); in set_gic_ctlr()
52 vmcr.cbpr = FIELD_GET(ICC_CTLR_EL1_CBPR_MASK, val); in set_gic_ctlr()
53 vmcr.eoim = FIELD_GET(ICC_CTLR_EL1_EOImode_MASK, val); in set_gic_ctlr()
64 u64 val; in get_gic_ctlr() local
67 val = 0; in get_gic_ctlr()
68 val |= FIELD_PREP(ICC_CTLR_EL1_PRI_BITS_MASK, vgic_v3_cpu->num_pri_bits - 1); in get_gic_ctlr()
[all …]
|
| D | nested.c | 30 u64 val, tmp; in access_nested_id_reg() local
32 val = p->regval; in access_nested_id_reg()
37 val &= ~(NV_FTR(ISAR0, TLB) | in access_nested_id_reg()
43 val &= ~(GENMASK_ULL(63, 56) | in access_nested_id_reg()
53 val &= ~(GENMASK_ULL(55, 52) | in access_nested_id_reg()
63 val |= FIELD_PREP(NV_FTR(PFR0, EL1), 0b0001); in access_nested_id_reg()
64 val |= FIELD_PREP(NV_FTR(PFR0, EL2), 0b0001); in access_nested_id_reg()
65 val |= FIELD_PREP(NV_FTR(PFR0, EL3), 0b0001); in access_nested_id_reg()
70 val &= NV_FTR(PFR1, SSBS); in access_nested_id_reg()
75 val &= ~(NV_FTR(MMFR0, ECV) | in access_nested_id_reg()
[all …]
|