| /drivers/gpu/drm/xe/ |
| D | xe_vm_doc.h | 1 /* SPDX-License-Identifier: MIT */
15 * Allocate a physical page for root of the page table structure, create default
19 * ------------
25 * VM bind (create GPU mapping for a BO or userptr)
28 * Creates GPU mappings for a BO or userptr within a VM. VM binds uses the same
33 * ----------
35 * DRM_XE_VM_BIND_OP_MAP - Create mapping for a BO
36 * DRM_XE_VM_BIND_OP_UNMAP - Destroy mapping for a BO / userptr
37 * DRM_XE_VM_BIND_OP_MAP_USERPTR - Create mapping for userptr
54 * .. code-block::
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| /drivers/gpu/drm/ci/ |
| D | gitlab-ci.yml | 2 DRM_CI_PROJECT_PATH: &drm-ci-project-path mesa/mesa
3 DRM_CI_COMMIT_SHA: &drm-ci-commit-sha d9849ac46623797a9f56fb9d46dc52460ac477de
6 TARGET_BRANCH: drm-next
10 DEQP_RUNNER_GIT_URL: https://gitlab.freedesktop.org/mesa/deqp-runner.git
13 FDO_UPSTREAM_REPO: helen.fornazier/linux # The repo where the git-archive daily runs
14 MESA_TEMPLATES_COMMIT: &ci-templates-commit d5aa3941aa03c2f716595116354fb81eb8012acb
16 CI_PRE_CLONE_SCRIPT: |-
17 set -o xtrace
18 …-L --retry 4 -f --retry-all-errors --retry-delay 60 -s ${DRM_CI_PROJECT_URL}/-/raw/${DRM_CI_COMMIT…
19 bash download-git-cache.sh
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| /drivers/gpu/drm/scheduler/ |
| D | sched_main.c | 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * The GPU scheduler provides entities which allow userspace to push jobs
28 * into software queues which are then scheduled on a hardware run queue.
31 * features among jobs. The driver is supposed to provide callback functions for
32 * backend operations to the scheduler like submitting a job to hardware run queue,
41 * 4. Entities themselves maintain a queue of jobs that will be scheduled on
42 * the hardware.
44 * The jobs in a entity are always scheduled in the order that they were pushed.
47 * hardware, i.e. the pending queue, the entity must not be referenced anymore
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| /drivers/media/platform/st/sti/hva/ |
| D | hva.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/videobuf2-v4l2.h>
14 #include <media/v4l2-mem2mem.h>
18 #define hva_to_dev(h) (h->dev)
20 #define ctx_to_dev(c) (c->hva_dev->dev)
22 #define ctx_to_hdev(c) (c->hva_dev)
24 #define HVA_NAME "st-hva"
25 #define HVA_PREFIX "[---:----]"
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| /drivers/crypto/caam/ |
| D | jr.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2008-2012 Freescale Semiconductor, Inc.
42 jrpriv->hwrng = !caam_rng_init(dev); in register_algs()
54 if (--active_devs != 0) in unregister_algs()
72 /* Free the resources of crypto-engine */ in caam_jr_crypto_engine_exit()
73 crypto_engine_exit(jrpriv->engine); in caam_jr_crypto_engine_exit()
87 if (rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_INPROGRESS) in caam_jr_stop_processing()
91 clrsetbits_32(&jrp->rregs->jrintstatus, JRINT_ERR_HALT_MASK, 0); in caam_jr_stop_processing()
93 /* initiate flush / park (required prior to reset) */ in caam_jr_stop_processing()
94 wr_reg32(&jrp->rregs->jrcommand, jrcr_bits); in caam_jr_stop_processing()
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| /drivers/gpu/drm/v3d/ |
| D | v3d_sched.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * The shared DRM GPU scheduler is used to coordinate submitting jobs
8 * to the hardware. Each DRM fd (roughly a client process) gets its
9 * own scheduler entity, which will process jobs in order. The GPU
10 * scheduler will round-robin between clients to submit the next job.
12 * For simplicity, and in order to keep latency low for interactive
13 * jobs when bulk background jobs are queued up, we submit a new job
15 * filling up the CT[01]Q FIFOs with jobs. Similarly, we use
17 * render, instead of having the clients submit jobs using the HW's
80 if (query_info->queries) { in v3d_timestamp_query_info_free()
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| /drivers/media/platform/renesas/ |
| D | rcar_fdp1.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Renesas R-Car Fine Display Processor
11 * m2m-deinterlace, and vsp1 drivers.
16 #include <linux/dma-mapping.h>
26 #include <media/rcar-fcp.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-event.h>
30 #include <media/v4l2-ioctl.h>
31 #include <media/v4l2-mem2mem.h>
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| /drivers/gpu/drm/imagination/ |
| D | pvr_device.c | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
21 #include <linux/dma-mapping.h>
33 /* Major number for the supported version of the firmware. */
37 * pvr_device_reg_init() - Initialize kernel access to a PowerVR device's
41 * Sets struct pvr_device->regs.
45 * required).
55 struct platform_device *plat_dev = to_platform_device(drm_dev->dev); in pvr_device_reg_init()
59 pvr_dev->regs_resource = NULL; in pvr_device_reg_init()
60 pvr_dev->regs = NULL; in pvr_device_reg_init()
64 return dev_err_probe(drm_dev->dev, PTR_ERR(regs), in pvr_device_reg_init()
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| /drivers/dma/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
21 This is an option for use by developers; most people should
28 This is an option for use by developers; most people should
65 Enable support for Altera / Intel mSGDMA controller.
86 Enable support for the AMCC PPC440SPe RAID engines.
94 Enable support for Audio DMA Controller found on Apple Silicon SoCs.
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
119 controller is often used in Analog Devices' reference designs for FPGA
132 Enable support for Broadcom SBA RAID Engine. The SBA RAID
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| D | ste_dma40.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Ericsson AB 2007-2008
4 * Copyright (C) ST-Ericsson SA 2008-2010
5 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
9 #include <linux/dma-mapping.h>
32 * struct stedma40_platform_data - Configuration struct for the dma device.
34 * @disabled_channels: A vector, ending with -1, that marks physical channels
35 * that are for different reasons not available for the driver.
38 * SoftLLI introduces relink overhead that could impact performance for
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| D | amba-pl08x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
17 * The PL080 has 8 channels available for simultaneous use, and the PL081
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
41 * For peripherals with a FIFO:
45 * (Bursts are irrelevant for mem to mem transfers - there are no burst
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| /drivers/gpu/drm/vc4/ |
| D | vc4_gem.c | 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
30 #include <linux/dma-fence-array.h>
44 mod_timer(&vc4->hangcheck.timer, in vc4_queue_hangcheck()
60 for (i = 0; i < state->user_state.bo_count; i++) in vc4_free_hang_state()
61 drm_gem_object_put(state->bo[i]); in vc4_free_hang_state()
79 if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5)) in vc4_get_hang_state_ioctl()
80 return -ENODEV; in vc4_get_hang_state_ioctl()
82 if (!vc4->v3d) { in vc4_get_hang_state_ioctl()
84 return -ENODEV; in vc4_get_hang_state_ioctl()
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| /drivers/gpu/drm/panthor/ |
| D | panthor_sched.c | 1 // SPDX-License-Identifier: GPL-2.0 or MIT
14 #include <linux/dma-mapping.h>
15 #include <linux/dma-resv.h>
20 #include <linux/iosys-map.h>
38 * Mali CSF hardware adopts a firmware-assisted scheduling model, where
42 * contains 1 to N queues (N is FW/hardware dependent, and exposed
44 * stream ring buffer, which serves as a way to get jobs submitted to
47 * The firmware can schedule a maximum of M groups (M is FW/hardware
51 * a chance to have his queues scheduled for execution.
53 * The current implementation only supports with kernel-mode queues.
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| /drivers/accel/habanalabs/common/ |
| D | habanalabs.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
64 * In device fini, wait 10 minutes for user processes to be terminated after we kill them.
95 /* Default value for device reset trigger , an invalid value */
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_device.c | 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
35 #include <linux/pci-p2pdma.h>
36 #include <linux/apple-gmux.h>
86 #include <asm/intel-family.h>
99 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
154 * The amdgpu driver provides a sysfs API for reporting the total number
156 * The file pcie_replay_count is used for this and returns the total
178 ret = sysfs_create_file(&adev->dev->kobj, in amdgpu_device_attr_sysfs_init()
187 sysfs_remove_file(&adev->dev->kobj, in amdgpu_device_attr_sysfs_fini()
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| D | vce_v3_0.c | 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
71 * vce_v3_0_ring_get_rptr - get read pointer
75 * Returns the current hardware read pointer
79 struct amdgpu_device *adev = ring->adev; in vce_v3_0_ring_get_rptr()
82 mutex_lock(&adev->grbm_idx_mutex); in vce_v3_0_ring_get_rptr()
83 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_rptr()
84 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_rptr()
86 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_rptr()
89 if (ring->me == 0) in vce_v3_0_ring_get_rptr()
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| D | amdgpu_psp.c | 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
58 struct amdgpu_device *adev = psp->adev; in psp_ring_init()
60 ring = &psp->km_ring; in psp_ring_init()
62 ring->ring_type = ring_type; in psp_ring_init()
64 /* allocate 4k Page of Local Frame Buffer memory for ring */ in psp_ring_init()
65 ring->ring_size = 0x1000; in psp_ring_init()
66 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, in psp_ring_init()
69 &adev->firmware.rbuf, in psp_ring_init()
70 &ring->ring_mem_mc_addr, in psp_ring_init()
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_drm.c | 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
101 int nouveau_modeset = -1;
108 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
109 static int nouveau_runtime_pm = -1;
119 u64 name = (u64)pci_domain_nr(pdev->bus) << 32; in nouveau_pci_name()
120 name |= pdev->bus->number << 16; in nouveau_pci_name()
121 name |= PCI_SLOT(pdev->devfn) << 8; in nouveau_pci_name()
122 return name | PCI_FUNC(pdev->devfn); in nouveau_pci_name()
128 return platformdev->id; in nouveau_platform_name()
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| /drivers/infiniband/hw/hfi1/ |
| D | pcie.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2019 Intel Corporation.
27 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
37 * Both reset cases set the BAR back to initial state. For in hfi1_pcie_init()
43 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
49 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
53 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in hfi1_pcie_init()
60 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in hfi1_pcie_init()
90 * fields required to re-initialize after a chip reset, or for
111 return -EINVAL; in hfi1_pcie_ddinit()
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| /drivers/net/wireless/intel/ipw2x00/ |
| D | ipw2100.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
12 Extensions 0.26 package and copyright (c) 1997-2003 Jean Tourrilhes
16 Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
18 Copyright (c) 2002-2003, Jouni Malinen <j@w1.fi>
34 Tx - Commands and Data
68 8) For each Tx interrupt received from the firmware, the READ index is checked
70 9) For each TBD that has been processed, the ISR pulls the oldest packet
77 The above steps are the same for commands, only the msg_free_list/msg_pend_list
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| /drivers/scsi/sym53c8xx_2/ |
| D | sym_hipd.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
4 * of PCI-SCSI IO processors.
6 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
7 * Copyright (c) 2003-2005 Matthew Wilcox <matthew@wil.cx>
10 * Copyright (C) 1998-2000 Gerard Roudier
13 * a port of the FreeBSD ncr driver to Linux-1.2.13.
15 * The original ncr driver has been written for 386bsd and FreeBSD by
17 * Stefan Esser <se@mi.Uni-Koeln.de>
25 *-----------------------------------------------------------------------------
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| /drivers/crypto/axis/ |
| D | artpec6_crypto.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for ARTPEC-6 crypto block using the kernel asynchronous crypto api.
5 * Copyright (C) 2014-2017 Axis Communications AB
13 #include <linux/dma-mapping.h>
14 #include <linux/fault-inject.h>
35 /* Max length of a line in all cache levels for Artpec SoCs. */
186 #define MODULE_NAME "Artpec-6 CA"
198 /* The PDMA is a DMA-engine tightly coupled with a ciphering engine.
203 * a 4-byte metadata that is inserted at the beginning of each dma packet.
208 * Multiple packets are used for providing context data, key data and
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| /drivers/isdn/hardware/mISDN/ |
| D | hfcmulti.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
7 * Peter Sprenger (sprengermoving-bytes.de)
9 * inspired by existing hfc-pci driver:
10 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
14 * Thanks to Cologne Chip AG for this great controller!
22 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
23 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
24 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
26 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
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