| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-phase.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-phase.h"
16 meson_clk_phase_data(struct clk_regmap *clk) in meson_clk_phase_data() argument
18 return (struct meson_clk_phase_data *)clk->data; in meson_clk_phase_data()
39 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_get_phase() local
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-mod0.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/sunxi/ |
| D | clk-mod0.c | 17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
23 #include "clk-factors.h"
26 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
37 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
38 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
40 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
53 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
54 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
55 req->p = calcp; in sun4i_a10_get_mod0_factors()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/meson/ |
| D | clk-triphase.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
8 #include "clkc-audio.h"
12 * The phase of mst_sclk clock output can be controlled independently
16 * If necessary, we can still control the phase in the tdm block
20 meson_clk_triphase_data(struct clk_regmap *clk) in meson_clk_triphase_data() argument
22 return (struct meson_clk_triphase_data *)clk->data; in meson_clk_triphase_data()
27 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_sync() local
28 struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk); in meson_clk_triphase_sync()
31 /* Get phase 0 and sync it to phase 1 and 2 */ in meson_clk_triphase_sync()
[all …]
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| D | clk-phase.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
13 meson_clk_phase_data(struct clk_regmap *clk) in meson_clk_phase_data() argument
15 return (struct meson_clk_phase_data *)clk->data; in meson_clk_phase_data()
38 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_get_phase() local
39 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
42 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
44 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
49 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_set_phase() local
50 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
[all …]
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-sirf.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/mmc/slot-gpio.h>
14 #include "sdhci-pltfm.h"
29 * 8bit-width enable bit of CSR SD hosts is 3, in sdhci_sirf_set_bus_width()
42 u32 val = readl(host->ioaddr + reg); in sdhci_sirf_readl_le()
45 (host->mmc->caps & MMC_CAP_UHS_SDR50))) { in sdhci_sirf_readl_le()
64 ret = readw(host->ioaddr + reg); in sdhci_sirf_readw_le()
67 ret = readw(host->ioaddr + SDHCI_HOST_VERSION); in sdhci_sirf_readw_le()
77 int phase; in sdhci_sirf_execute_tuning() local
80 int start = -1, end = 0, tuning_value = -1, range = 0; in sdhci_sirf_execute_tuning()
[all …]
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| D | mmci_stm32_sdmmc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
64 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
65 if (!IS_ALIGNED(data->sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
66 !IS_ALIGNED(data->sg->length, SDMMC_IDMA_BURST)) { in sdmmc_idma_validate_data()
67 dev_err(mmc_dev(host->mmc), in sdmmc_idma_validate_data()
69 data->sg->offset, data->sg->length); in sdmmc_idma_validate_data()
70 return -EINVAL; in sdmmc_idma_validate_data()
74 if (!IS_ALIGNED(data->sg->offset, sizeof(u32))) { in sdmmc_idma_validate_data()
[all …]
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| D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
68 * @shift: Bit offset within @reg of this field (or -1 if not avail)
[all …]
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| D | sdhci-msm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
20 #include "sdhci-pltfm.h"
119 #define INVALID_TUNING_PHASE -1
133 /* Max load for eMMC Vdd-io supply */
137 msm_host->var_ops->msm_readl_relaxed(host, offset)
140 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
260 struct clk *bus_clk; /* SDHC bus voter clock */
261 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
[all …]
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| D | dw_mmc-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
21 struct clk *drv_clk;
22 struct clk *sample_clk;
29 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
34 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
41 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
44 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
[all …]
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| /kernel/linux/linux-5.10/include/trace/events/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #define TRACE_SYSTEM clk
15 DECLARE_EVENT_CLASS(clk,
22 __string( name, core->name )
26 __assign_str(name, core->name);
32 DEFINE_EVENT(clk, clk_enable,
39 DEFINE_EVENT(clk, clk_enable_complete,
46 DEFINE_EVENT(clk, clk_disable,
53 DEFINE_EVENT(clk, clk_disable_complete,
[all …]
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| /kernel/linux/linux-4.19/drivers/mmc/host/ |
| D | sdhci-sirf.c | 15 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
35 * 8bit-width enable bit of CSR SD hosts is 3, in sdhci_sirf_set_bus_width()
48 u32 val = readl(host->ioaddr + reg); in sdhci_sirf_readl_le()
51 (host->mmc->caps & MMC_CAP_UHS_SDR50))) { in sdhci_sirf_readl_le()
70 ret = readw(host->ioaddr + reg); in sdhci_sirf_readw_le()
73 ret = readw(host->ioaddr + SDHCI_HOST_VERSION); in sdhci_sirf_readw_le()
83 int phase; in sdhci_sirf_execute_tuning() local
86 int start = -1, end = 0, tuning_value = -1, range = 0; in sdhci_sirf_execute_tuning()
88 struct mmc_host *mmc = host->mmc; in sdhci_sirf_execute_tuning()
[all …]
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| D | sdhci-msm.c | 2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
26 #include "sdhci-pltfm.h"
114 #define INVALID_TUNING_PHASE -1
129 msm_host->var_ops->msm_readl_relaxed(host, offset)
132 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
244 struct clk *bus_clk; /* SDHC bus voter clock */
245 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
272 return msm_host->offset; in sdhci_priv_msm_offset()
285 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
[all …]
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| D | dw_mmc-rockchip.c | 12 #include <linux/clk.h>
15 #include <linux/mmc/slot-gpio.h>
20 #include "dw_mmc-pltfm.h"
25 struct clk *drv_clk;
26 struct clk *sample_clk;
33 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
38 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
45 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
48 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
50 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
[all …]
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| /kernel/linux/linux-4.19/include/trace/events/ |
| D | clk.h | 2 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
14 #define TRACE_SYSTEM clk
23 DECLARE_EVENT_CLASS(clk,
30 __string( name, core->name )
34 __assign_str(name, core->name);
40 DEFINE_EVENT(clk, clk_enable,
47 DEFINE_EVENT(clk, clk_enable_complete,
54 DEFINE_EVENT(clk, clk_disable,
61 DEFINE_EVENT(clk, clk_disable_complete,
68 DEFINE_EVENT(clk, clk_prepare,
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-mmc-phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
12 #include "clk.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
54 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
86 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
97 pr_err("%s: invalid clk rate\n", __func__); in rockchip_mmc_set_phase()
98 return -EINVAL; in rockchip_mmc_set_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/hisilicon/ |
| D | clk-hisi-phase.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Simple HiSilicon phase clock implementation.
14 #include "clk.h"
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
39 return -EINVAL; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/hisilicon/ |
| D | clk-hisi-phase.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Simple HiSilicon phase clock implementation.
14 #include "clk.h"
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
39 return -EINVAL; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | altr_socfpga.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | altr_socfpga.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/rockchip/ |
| D | clk-mmc-phase.c | 17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
21 #include "clk.h"
50 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
58 unsigned long rate = clk_get_rate(hw->clk); in rockchip_mmc_get_phase()
65 return -EINVAL; in rockchip_mmc_get_phase()
67 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
87 unsigned long rate = clk_get_rate(hw->clk); in rockchip_mmc_set_phase()
95 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
106 pr_err("%s: invalid clk rate\n", __func__); in rockchip_mmc_set_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
81 int phase; member
95 #include <trace/events/clk.h>
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dccg.c | 36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
45 dccg->ctx->logger
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
53 int modulo, phase; in dccg2_update_dpp_dto() local
55 // phase / modulo = dpp pipe clk / dpp global clk in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
59 if (phase > 0xff) { in dccg2_update_dpp_dto()
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/spi/ |
| D | spi-samsung.txt | 8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-samsung.txt | 8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
[all …]
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