| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3556av100/ |
| D | lowlevel_init_v300.c | 64 #define DDR_REG_BASE_DMC3 0x0460b000 macro
275 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3519av100/ |
| D | ddr_training_custom.h | 59 #define DDR_REG_BASE_DMC3 0x0460b000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3556av100/ |
| D | ddr_training_custom.h | 60 #define DDR_REG_BASE_DMC3 0x0460b000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv300/ |
| D | ddr_training_custom.h | 58 #define DDR_REG_BASE_DMC3 0x1206b000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516av300/ |
| D | ddr_training_custom.h | 58 #define DDR_REG_BASE_DMC3 0x1206b000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3559av100/ |
| D | ddr_training_custom.h | 53 #define DDR_REG_BASE_DMC3 0x1206b000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516cv500/ |
| D | ddr_training_custom.h | 58 #define DDR_REG_BASE_DMC3 0x1206b000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev200/ |
| D | ddr_training_custom.h | 59 #define DDR_REG_BASE_DMC3 0x120d9000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev300/ |
| D | ddr_training_custom.h | 59 #define DDR_REG_BASE_DMC3 0x120d9000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3518ev300/ |
| D | ddr_training_custom.h | 59 #define DDR_REG_BASE_DMC3 0x120d9000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv200/ |
| D | ddr_training_custom.h | 59 #define DDR_REG_BASE_DMC3 0x120d9000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3520dv500/ |
| D | ddr_training_custom.h | 48 #define DDR_REG_BASE_DMC3 0x1113b000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3521dv200/ |
| D | ddr_training_custom.h | 48 #define DDR_REG_BASE_DMC3 0x1113b000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3535av100/ |
| D | ddr_training_custom.h | 48 #define DDR_REG_BASE_DMC3 0x1113b000 macro
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3531dv200/ |
| D | ddr_training_custom.h | 48 #define DDR_REG_BASE_DMC3 0x1113b000 macro
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/ |
| D | lowlevel_init_v300.c | 288 #define DDR_REG_BASE_DMC3 0x120d9000 macro
443 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/ |
| D | lowlevel_init_v300.c | 284 #define DDR_REG_BASE_DMC3 0x120d9000 macro
439 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/ |
| D | lowlevel_init_v300.c | 287 #define DDR_REG_BASE_DMC3 0x120d9000 macro
442 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/ |
| D | lowlevel_init_v300.c | 289 #define DDR_REG_BASE_DMC3 0x120d9000 macro
445 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516av300/ |
| D | lowlevel_init_v300.c | 446 #define DDR_REG_BASE_DMC3 0x1206b000 macro
478 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516cv500/ |
| D | lowlevel_init_v300.c | 448 #define DDR_REG_BASE_DMC3 0x1206b000 macro
480 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv300/ |
| D | lowlevel_init_v300.c | 446 #define DDR_REG_BASE_DMC3 0x1206b000 macro
478 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3519av100/ |
| D | lowlevel_init_v300.c | 62 #define DDR_REG_BASE_DMC3 0x0460b000 macro
561 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3569v100/ |
| D | lowlevel_init_v300.c | 58 #define DDR_REG_BASE_DMC3 0x1206b000 macro
698 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3559av100/ |
| D | lowlevel_init_v300.c | 58 #define DDR_REG_BASE_DMC3 0x1206b000 macro
698 writel(0x401, DDR_REG_BASE_DMC3 + 0x28); in start_ddr_training()
|