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Searched refs:iomux (Results 1 – 25 of 66) sorted by relevance

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/third_party/uboot/u-boot-2020.01/drivers/pinctrl/nxp/
Dpinctrl-mxs.c45 struct mxs_pinctrl_priv *iomux = dev_get_priv(dev); in mxs_pinctrl_set_mux() local
49 reg = iomux->base + iomux->regs->muxsel; in mxs_pinctrl_set_mux()
61 struct mxs_pinctrl_priv *iomux = dev_get_priv(dev); in mxs_pinctrl_set_state() local
114 reg = iomux->base + iomux->regs->drive; in mxs_pinctrl_set_state()
134 reg = iomux->base + iomux->regs->pull; in mxs_pinctrl_set_state()
154 struct mxs_pinctrl_priv *iomux = dev_get_priv(dev); in mxs_pinctrl_probe() local
156 iomux->base = dev_read_addr_ptr(dev); in mxs_pinctrl_probe()
157 iomux->regs = (struct mxs_regs *)dev_get_driver_data(dev); in mxs_pinctrl_probe()
/third_party/uboot/u-boot-2020.01/drivers/pinctrl/rockchip/
Dpinctrl-rockchip.h95 struct rockchip_iomux iomux[4]; member
107 .iomux = { \
120 .iomux = { \
133 .iomux = { \
154 .iomux = { \
180 .iomux = { \
204 .iomux = { \
Dpinctrl-rk3036.c23 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3036_set_mux()
27 mux_type = bank->iomux[iomux_num].type; in rk3036_set_mux()
28 reg = bank->iomux[iomux_num].offset; in rk3036_set_mux()
Dpinctrl-rockchip-core.c123 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
128 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
131 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
135 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
136 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
165 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
170 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
204 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
505 struct rockchip_iomux *iom = &bank->iomux[j];
Dpinctrl-rk3188.c23 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3188_set_mux()
27 mux_type = bank->iomux[iomux_num].type; in rk3188_set_mux()
28 reg = bank->iomux[iomux_num].offset; in rk3188_set_mux()
Dpinctrl-rk3368.c23 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3368_set_mux()
27 mux_type = bank->iomux[iomux_num].type; in rk3368_set_mux()
28 reg = bank->iomux[iomux_num].offset; in rk3368_set_mux()
Dpinctrl-rk3128.c110 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3128_set_mux()
114 mux_type = bank->iomux[iomux_num].type; in rk3128_set_mux()
115 reg = bank->iomux[iomux_num].offset; in rk3128_set_mux()
Dpinctrl-rk3288.c40 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3288_set_mux()
44 mux_type = bank->iomux[iomux_num].type; in rk3288_set_mux()
45 reg = bank->iomux[iomux_num].offset; in rk3288_set_mux()
Dpinctrl-rk322x.c153 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3228_set_mux()
157 mux_type = bank->iomux[iomux_num].type; in rk3228_set_mux()
158 reg = bank->iomux[iomux_num].offset; in rk3228_set_mux()
Dpinctrl-rk3399.c62 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3399_set_mux()
66 mux_type = bank->iomux[iomux_num].type; in rk3399_set_mux()
67 reg = bank->iomux[iomux_num].offset; in rk3399_set_mux()
Dpinctrl-rv1108.c87 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rv1108_set_mux()
91 mux_type = bank->iomux[iomux_num].type; in rv1108_set_mux()
92 reg = bank->iomux[iomux_num].offset; in rv1108_set_mux()
/third_party/uboot/u-boot-2020.01/board/technexion/pico-imx6/
Dpico-imx6.c140 struct iomuxc *iomux = (struct iomuxc *) in enable_lvds() local
144 u32 reg = readl(&iomux->gpr[2]); in enable_lvds()
146 writel(reg, &iomux->gpr[2]); in enable_lvds()
234 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display() local
279 writel(reg, &iomux->gpr[2]); in setup_display()
280 reg = readl(&iomux->gpr[3]); in setup_display()
287 writel(reg, &iomux->gpr[3]); in setup_display()
/third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/
Dcache.c85 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in v7_outer_cache_enable() local
103 val = readl(&iomux->gpr[11]); in v7_outer_cache_enable()
107 writel(val, &iomux->gpr[11]); in v7_outer_cache_enable()
/third_party/uboot/u-boot-2020.01/board/engicam/imx6q/
Dimx6q.c144 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display() local
180 writel(reg, &iomux->gpr[2]); in setup_display()
182 reg = readl(&iomux->gpr[3]); in setup_display()
186 writel(reg, &iomux->gpr[3]); in setup_display()
/third_party/uboot/u-boot-2020.01/board/aristainetos/
Daristainetos-v2.c407 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in enable_lvds() local
467 writel(reg, &iomux->gpr[2]); in enable_lvds()
469 reg = readl(&iomux->gpr[3]); in enable_lvds()
473 writel(reg, &iomux->gpr[3]); in enable_lvds()
480 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in enable_spi_display() local
559 writel(reg, &iomux->gpr[2]); in enable_spi_display()
561 reg = readl(&iomux->gpr[3]); in enable_spi_display()
565 writel(reg, &iomux->gpr[3]); in enable_spi_display()
/third_party/uboot/u-boot-2020.01/board/embest/mx6boards/
Dmx6boards.c380 struct iomuxc *iomux = (struct iomuxc *) in enable_lvds() local
382 setbits_le32(&iomux->gpr[2], in enable_lvds()
393 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in disable_lvds() local
401 clrbits_le32(&iomux->gpr[2], in disable_lvds()
463 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display() local
493 writel(reg, &iomux->gpr[2]); in setup_display()
495 clrsetbits_le32(&iomux->gpr[3], in setup_display()
/third_party/uboot/u-boot-2020.01/doc/device-tree-bindings/pinctrl/
Drockchip,pinctrl.txt21 Required properties for iomux controller:
28 Optional properties for iomux controller:
30 as some SoCs carry parts of the iomux controller registers there.
33 Deprecated properties for iomux controller:
34 - reg: first element is the general register space of the iomux controller
41 - reg: register of the gpio bank (different than the iomux registerset)
/third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx6/
Dsoc.c700 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in gpr_init() local
711 writel(0xF00000CF, &iomux->gpr[4]); in gpr_init()
714 writel(0x77177717, &iomux->gpr[6]); in gpr_init()
715 writel(0x77177717, &iomux->gpr[7]); in gpr_init()
718 writel(0x007F007F, &iomux->gpr[6]); in gpr_init()
719 writel(0x007F007F, &iomux->gpr[7]); in gpr_init()
/third_party/uboot/u-boot-2020.01/board/ge/mx53ppd/
Dmx53ppd_video.c80 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in lcd_enable() local
98 &iomux->gpr[2]); in lcd_enable()
/third_party/uboot/u-boot-2020.01/board/boundary/nitrogen6x/
Dnitrogen6x.c502 struct iomuxc *iomux = (struct iomuxc *) in enable_lvds() local
504 u32 reg = readl(&iomux->gpr[2]); in enable_lvds()
506 writel(reg, &iomux->gpr[2]); in enable_lvds()
512 struct iomuxc *iomux = (struct iomuxc *) in enable_lvds_jeida() local
514 u32 reg = readl(&iomux->gpr[2]); in enable_lvds_jeida()
517 writel(reg, &iomux->gpr[2]); in enable_lvds_jeida()
778 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display() local
814 writel(reg, &iomux->gpr[2]); in setup_display()
816 reg = readl(&iomux->gpr[3]); in setup_display()
821 writel(reg, &iomux->gpr[3]); in setup_display()
/third_party/uboot/u-boot-2020.01/board/ge/bx50v3/
Dbx50v3.c325 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display_b850v3() local
355 &iomux->gpr[2]); in setup_display_b850v3()
357 clrbits_le32(&iomux->gpr[3], in setup_display_b850v3()
366 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display_bx50v3() local
396 &iomux->gpr[2]); in setup_display_bx50v3()
398 clrsetbits_le32(&iomux->gpr[3], in setup_display_bx50v3()
/third_party/uboot/u-boot-2020.01/board/freescale/mx6sabresd/
Dmx6sabresd.c364 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in disable_lvds() local
366 int reg = readl(&iomux->gpr[2]); in disable_lvds()
371 writel(reg, &iomux->gpr[2]); in disable_lvds()
446 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display() local
488 writel(reg, &iomux->gpr[2]); in setup_display()
490 reg = readl(&iomux->gpr[3]); in setup_display()
495 writel(reg, &iomux->gpr[3]); in setup_display()
/third_party/uboot/u-boot-2020.01/board/kosagi/novena/
Dvideo.c388 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display_clock() local
421 &iomux->gpr[2]); in setup_display_clock()
423 clrsetbits_le32(&iomux->gpr[3], in setup_display_clock()
/third_party/uboot/u-boot-2020.01/board/freescale/mx6sabreauto/
Dmx6sabreauto.c406 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in disable_lvds() local
408 clrbits_le32(&iomux->gpr[2], in disable_lvds()
476 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display() local
515 writel(reg, &iomux->gpr[2]); in setup_display()
517 reg = readl(&iomux->gpr[3]); in setup_display()
524 writel(reg, &iomux->gpr[3]); in setup_display()
/third_party/uboot/u-boot-2020.01/board/freescale/mx28evk/
DMakefile9 obj-y := iomux.o

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