Home
last modified time | relevance | path

Searched refs:mxc_ccm (Results 1 – 25 of 34) sorted by relevance

12

/third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx5/
Dclock.c73 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; variable
77 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk()
80 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk()
91 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk()
111 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
113 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
120 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); in set_usb_phy_clk()
128 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usb_phy1_clk()
142 clrsetbits_le32(&mxc_ccm->CCGR4, in enable_usb_phy1_clk()
151 clrsetbits_le32(&mxc_ccm->CCGR4, in enable_usb_phy2_clk()
[all …]
/third_party/uboot/u-boot-2020.01/board/engicam/imx6q/
Dimx6q.c50 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
56 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
59 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
68 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
71 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
79 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
143 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
150 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
152 writel(reg, &mxc_ccm->CCGR3); in setup_display()
155 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx6/
Dclock.c1281 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in enable_ipu_clock() local
1283 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK); in enable_ipu_clock()
1286 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); in enable_ipu_clock()
1287 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); in enable_ipu_clock()
1293 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in disable_ipu_clock() local
1295 clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK); in disable_ipu_clock()
1298 clrbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); in disable_ipu_clock()
1299 clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); in disable_ipu_clock()
1344 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in disable_ldb_di_clock_sources() local
1348 reg = readl(&mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
[all …]
Dsoc.c304 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in set_ahb_rate() local
308 reg = readl(&mxc_ccm->cbcdr); in set_ahb_rate()
311 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); in set_ahb_rate()
316 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in clear_mmdc_ch_mask() local
318 reg = readl(&mxc_ccm->ccdr); in clear_mmdc_ch_mask()
325 writel(reg, &mxc_ccm->ccdr); in clear_mmdc_ch_mask()
660 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in imx_setup_hdmi() local
666 reg = readl(&mxc_ccm->CCGR2); in imx_setup_hdmi()
669 writel(reg, &mxc_ccm->CCGR2); in imx_setup_hdmi()
671 reg = readl(&mxc_ccm->chsccdr); in imx_setup_hdmi()
[all …]
/third_party/uboot/u-boot-2020.01/board/engicam/imx6ul/
Dimx6ul.c51 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
56 clrbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
68 clrbits_le32(&mxc_ccm->cscmr1, in setup_gpmi_nand()
71 clrsetbits_le32(&mxc_ccm->cscdr1, in setup_gpmi_nand()
78 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
86 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/third_party/uboot/u-boot-2020.01/board/technexion/pico-imx6/
Dpico-imx6.c233 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
247 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
249 writel(reg, &mxc_ccm->CCGR3); in setup_display()
252 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
257 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
259 reg = readl(&mxc_ccm->cscmr2); in setup_display()
261 writel(reg, &mxc_ccm->cscmr2); in setup_display()
263 reg = readl(&mxc_ccm->chsccdr); in setup_display()
268 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/third_party/uboot/u-boot-2020.01/board/ge/mx53ppd/
Dmx53ppd_video.c79 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in lcd_enable() local
83 clrsetbits_le32(&mxc_ccm->cscmr2, in lcd_enable()
89 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3)); in lcd_enable()
92 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3)); in lcd_enable()
/third_party/uboot/u-boot-2020.01/board/variscite/dart_6ul/
Ddart_6ul.c55 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
60 clrbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
72 clrbits_le32(&mxc_ccm->cscmr1, in setup_gpmi_nand()
75 clrsetbits_le32(&mxc_ccm->cscdr1, in setup_gpmi_nand()
82 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
90 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/third_party/uboot/u-boot-2020.01/board/aristainetos/
Daristainetos.c232 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
239 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
242 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
251 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
254 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
262 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
Daristainetos-v1.c221 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
226 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
230 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
/third_party/uboot/u-boot-2020.01/board/barco/platinum/
Dplatinum.c65 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
71 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
80 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
88 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/third_party/uboot/u-boot-2020.01/board/freescale/mx6sabreauto/
Dmx6sabreauto.c329 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
339 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
475 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
484 reg = readl(&mxc_ccm->CCGR3); in setup_display()
486 writel(reg, &mxc_ccm->CCGR3); in setup_display()
489 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
494 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
496 reg = readl(&mxc_ccm->cscmr2); in setup_display()
498 writel(reg, &mxc_ccm->cscmr2); in setup_display()
500 reg = readl(&mxc_ccm->chsccdr); in setup_display()
[all …]
/third_party/uboot/u-boot-2020.01/board/kosagi/novena/
Dvideo.c387 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display_clock() local
395 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_clock()
398 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_display_clock()
403 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_clock()
406 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_clock()
/third_party/uboot/u-boot-2020.01/board/ge/bx50v3/
Dbx50v3.c324 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display_b850v3() local
330 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_b850v3()
335 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_b850v3()
341 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_b850v3()
365 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display_bx50v3() local
378 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_bx50v3()
381 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_bx50v3()
387 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_bx50v3()
/third_party/uboot/u-boot-2020.01/board/freescale/mx6sabresd/
Dmx6sabresd.c445 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
456 reg = readl(&mxc_ccm->CCGR3); in setup_display()
458 writel(reg, &mxc_ccm->CCGR3); in setup_display()
461 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
466 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
468 reg = readl(&mxc_ccm->cscmr2); in setup_display()
470 writel(reg, &mxc_ccm->cscmr2); in setup_display()
472 reg = readl(&mxc_ccm->chsccdr); in setup_display()
477 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/third_party/uboot/u-boot-2020.01/board/phytec/pcm058/
Dpcm058.c293 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
299 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
302 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
311 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
314 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
322 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/third_party/uboot/u-boot-2020.01/board/barco/titanium/
Dtitanium.c158 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
165 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
174 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
182 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/third_party/uboot/u-boot-2020.01/board/gateworks/gw_ventana/
Dgw_ventana.c101 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
107 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
116 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
124 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
455 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
462 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
464 writel(reg, &mxc_ccm->CCGR3); in setup_display()
467 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
472 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
474 reg = readl(&mxc_ccm->cscmr2); in setup_display()
[all …]
/third_party/uboot/u-boot-2020.01/board/toradex/colibri_imx6/
Dcolibri_imx6.c548 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
555 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
557 writel(reg, &mxc_ccm->CCGR3); in setup_display()
560 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
565 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
567 reg = readl(&mxc_ccm->cscmr2); in setup_display()
569 writel(reg, &mxc_ccm->cscmr2); in setup_display()
571 reg = readl(&mxc_ccm->chsccdr); in setup_display()
574 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/third_party/uboot/u-boot-2020.01/board/k+p/kp_imx6q_tpc/
Dkp_imx6q_tpc.c112 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in board_init() local
118 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); in board_init()
/third_party/uboot/u-boot-2020.01/board/phytec/pfla02/
Dpfla02.c277 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
283 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
286 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
295 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
298 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
306 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/third_party/uboot/u-boot-2020.01/board/toradex/apalis_imx6/
Dapalis_imx6.c584 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
591 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
593 writel(reg, &mxc_ccm->CCGR3); in setup_display()
596 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
601 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
603 reg = readl(&mxc_ccm->cscmr2); in setup_display()
605 writel(reg, &mxc_ccm->cscmr2); in setup_display()
607 reg = readl(&mxc_ccm->chsccdr); in setup_display()
610 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/third_party/uboot/u-boot-2020.01/board/boundary/nitrogen6x/
Dnitrogen6x.c777 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
784 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
786 writel(reg, &mxc_ccm->CCGR3); in setup_display()
789 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
794 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
796 reg = readl(&mxc_ccm->cscmr2); in setup_display()
798 writel(reg, &mxc_ccm->cscmr2); in setup_display()
800 reg = readl(&mxc_ccm->chsccdr); in setup_display()
803 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/third_party/uboot/u-boot-2020.01/board/embest/mx6boards/
Dmx6boards.c462 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
470 setbits_le32(&mxc_ccm->CCGR3, in setup_display()
474 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_display()
478 setbits_le32(&mxc_ccm->cscmr2, in setup_display()
481 setbits_le32(&mxc_ccm->chsccdr, in setup_display()
/third_party/uboot/u-boot-2020.01/board/dhelectronics/dh_imx6/
Ddh_imx6.c183 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in board_init() local
189 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); in board_init()

12