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/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4a/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/SuperH SH-4 backends.
7 obj-$(CONFIG_CPU_SUBTYPE_SH7757) += setup-sh7757.o
8 obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
9 obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
10 obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
11 obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
12 obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o
13 obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
14 obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/qcom/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 select PINMUX
18 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
26 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
34 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
42 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
50 This is the pinctrl, pinmux, pinconf and gpiolib driver for
60 This is the pinctrl, pinmux, pinconf and gpiolib driver for
70 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
79 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dstm32mp15-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 adc1_in6_pins_a: adc1-in6-0 {
11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
15 adc12_ain_pins_a: adc12-ain-0 {
17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
24 adc12_ain_pins_b: adc12-ain-1 {
26 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
[all …]
Dat91-sama5d27_som1_ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board
10 /dts-v1/;
11 #include "at91-sama5d27_som1.dtsi"
12 #include <dt-bindings/mfd/atmel-flexcom.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
18 …compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "…
29 stdout-path = "serial0:115200n8";
34 atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>;
[all …]
Dat91-sama5d2_icp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board
11 /dts-v1/;
13 #include "sama5d2-pinfunc.h"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
19 model = "Microchip SAMA5D2-ICP";
20 compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
32 stdout-path = "serial0:115200n8";
[all …]
Dimx28.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include "imx28-pinfunc.h"
9 #address-cells = <1>;
10 #size-cells = <1>;
12 interrupt-parent = <&icoll>;
15 * pre-existing /chosen node to be available to insert the
42 #address-cells = <1>;
43 #size-cells = <0>;
46 compatible = "arm,arm926ej-s";
[all …]
Dat91-sama5d2_xplained.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board
8 /dts-v1/;
10 #include "sama5d2-pinfunc.h"
11 #include <dt-bindings/mfd/atmel-flexcom.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/regulator/active-semi,8945a-regulator.h>
18 compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";
28 stdout-path = "serial0:115200n8";
[all …]
Dat91-sama5d2_ptc_ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
3 * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board
9 /dts-v1/;
11 #include "sama5d2-pinfunc.h"
12 #include <dt-bindings/mfd/atmel-flexcom.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/pinctrl/at91.h>
19 compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
29 stdout-path = "serial0:115200n8";
[all …]
Dat91-kizbox3_common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3
12 /dts-v1/;
14 #include "sama5d2-pinfunc.h"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
17 #include <dt-bindings/pinctrl/at91.h>
18 #include <dt-bindings/pwm/pwm.h>
36 stdout-path = "serial1:115200n8";
41 clock-frequency = <32768>;
[all …]
Dat91-sama5d27_wlsom1_ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
9 /dts-v1/;
10 #include "at91-sama5d27_wlsom1.dtsi"
11 #include <dt-bindings/input/input.h>
15 …compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel…
26 stdout-path = "serial0:115200n8";
30 compatible = "gpio-keys";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_key_gpio_default>;
[all …]
Dat91-kizbox3-hs.dts1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board
11 /dts-v1/;
12 #include "at91-kizbox3_common.dtsi"
15 model = "Overkiz KIZBOX3-HS";
16 compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5";
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_led_red
48 default-state = "off";
[all …]
Dstm32f7-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rcc.h>
12 pinctrl: pin-controller {
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&exti>;
18 pins-are-numbered;
21 gpio-controller;
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 config PINMUX config
19 select PINMUX
35 bool "Axis ARTPEC-6 pin controller driver"
37 select PINMUX
40 This is the driver for the Axis ARTPEC-6 pin controller. This driver
43 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
48 select PINMUX
52 functionality. This driver supports the pinmux, push-pull and
57 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt8183-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
14 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
26 stdout-path = "serial0:921600n8";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
34 compatible = "shared-dma-pool";
36 no-map;
46 pinctrl-names = "default";
[all …]
Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
19 stdout-path = "serial0:115200n8";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
31 clock-output-names = "clk32k";
35 compatible = "regulator-fixed";
36 regulator-name = "it6505_pp18";
[all …]
Dmt8173-elm.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/regulator/dlg,da9211-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
19 compatible = "pwm-backlight";
21 power-supply = <&bl_fixed_reg>;
22 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&disp_pwm0_pins>;
[all …]
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2a/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/SuperH SH-2A backends.
6 obj-y := common.o probe.o opcode_helper.o
8 common-y += ex.o entry.o
10 obj-$(CONFIG_SH_FPU) += fpu.o
12 obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o
13 obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
14 obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
15 obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o
16 obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dmsm8996-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
17 drive-strength = <2>; /* 2 mA */
18 bias-pull-down; /* pull down */
19 input-enable;
32 drive-strength = <16>;
33 bias-disable;
34 output-low;
44 drive-strength = <16>;
45 bias-pull-down;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra124-pinmux.txt1 NVIDIA Tegra124 pinmux controller
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
10 Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
11 - reg: Should contain a list of base address and size pairs for:
12 -- first entry - the drive strength and pad control registers.
13 -- second entry - the pinmux registers
14 -- third entry - the MIPI_PAD_CTRL register
18 include/dt-binding/pinctrl/pinctrl-tegra.h.
[all …]
Dnvidia,tegra194-pinmux.txt1 NVIDIA Tegra194 pinmux controller
4 - compatible: "nvidia,tegra194-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
17 parameters, such as pull-up, tristate, drive strength, etc.
21 include/dt-binding/pinctrl/pinctrl-tegra.h.
23 Required subnode-properties:
24 - nvidia,pins : An array of strings. Each string contains the name of a pin or
[all …]
Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
50 For cases like this, the pin controller driver may use pinctrl-pin-array helper
55 #pinctrl-cells = <2>;
58 pinctrl-pin-array = <
67 Above #pinctrl-cells specifies the number of value cells in addition to the
68 index of the registers. This is similar to the interrupts-extended binding with
[all …]
Dpinctrl-mt65xx.txt6 - compatible: value should be one of the following.
7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
8 "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
9 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
10 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
13 "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
14 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
15 "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
[all …]
Dnvidia,tegra114-pinmux.txt1 NVIDIA Tegra114 pinmux controller
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: "nvidia,tegra114-pinmux"
10 - reg: Should contain the register physical address and length for each of
13 be pinmux register address.
16 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
17 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
18 - nvidia,lock: Integer. Lock the pin configuration against further changes
20 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
[all …]
Dpinctrl-zx.txt10 GMII_RXD3 ---+
12 DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
14 BGPIO16 ---+ ^
17 | pinmux |
23 | pinmux | |
24 | pinmux v |
26 KEY_ROW2 ---+ v
27 PORT1_LCD_TE ---+ |
28 | AGPIO10 ---+------ KEY_ROW2 (AON pin)
29 I2S0_DOUT3 ---+ |
[all …]
Dintel,lgm-io.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
[all …]

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