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Searched refs:GENMASK (Results 1 – 25 of 135) sorted by relevance

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/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/
Dmali_kbase_l2_mmu_config.c66 {GPU_ID2_PRODUCT_LBEX, {0, GENMASK(10, 5), 5}, {0, GENMASK(16, 12), 12}},
67 {GPU_ID2_PRODUCT_TBEX, {0, GENMASK(10, 5), 5}, {0, GENMASK(16, 12), 12}},
68 {GPU_ID2_PRODUCT_TBAX, {0, GENMASK(10, 5), 5}, {0, GENMASK(16, 12), 12}},
69 {GPU_ID2_PRODUCT_TTRX, {0, GENMASK(12, 7), 7}, {0, GENMASK(17, 13), 13}},
70 {GPU_ID2_PRODUCT_TNAX, {0, GENMASK(12, 7), 7}, {0, GENMASK(17, 13), 13}},
71 …{GPU_ID2_PRODUCT_TGOX, {KBASE_3BIT_AID_32, GENMASK(14, 12), 12}, {KBASE_3BIT_AID_32, GENMASK(17, 1…
72 …{GPU_ID2_PRODUCT_TNOX, {KBASE_3BIT_AID_32, GENMASK(14, 12), 12}, {KBASE_3BIT_AID_32, GENMASK(17, 1…
79 {KBASE_AID_32, GENMASK(25, 24), 24}, in kbase_set_mmu_quirks()
80 {KBASE_AID_32, GENMASK(27, 26), 26}}; in kbase_set_mmu_quirks()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
Dmali_kbase_l2_mmu_config.c65 {0, GENMASK(10, 5), 5},
66 {0, GENMASK(16, 12), 12} },
68 {0, GENMASK(10, 5), 5},
69 {0, GENMASK(16, 12), 12} },
71 {0, GENMASK(10, 5), 5},
72 {0, GENMASK(16, 12), 12} },
74 {0, GENMASK(12, 7), 7},
75 {0, GENMASK(17, 13), 13} },
77 {0, GENMASK(12, 7), 7},
78 {0, GENMASK(17, 13), 13} },
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/device/soc/amlogic/a311d/soc/include/linux/amlogic/
Daml_sd.h214 #define CLK_DIV_MASK GENMASK(5, 0)
215 #define CLK_SRC_MASK GENMASK(7, 6)
216 #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
217 #define CLK_TX_PHASE_MASK GENMASK(11, 10)
218 #define CLK_RX_PHASE_MASK GENMASK(13, 12)
221 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
222 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
225 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
226 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
238 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
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/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
Dphy-rockchip-samsung-hdptx.c20 #define RO_REF_CLK_SEL GENMASK(11, 10)
21 #define LC_REF_CLK_SEL GENMASK(9, 8)
44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0)
48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3)
49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0)
55 #define ROPLL_PMS_MDIV GENMASK(7, 0)
58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0)
61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0)
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Dphy-rockchip-naneng-combphy.c100 mask = GENMASK(reg->bitend, reg->bitstart); in param_read()
112 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
123 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
337 (GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1])); in rockchip_combphy_parse_dt()
444 val &= ~GENMASK(5, 4); in rk3568_combphy_cfg()
456 val &= ~GENMASK(5, 4); in rk3568_combphy_cfg()
462 val &= ~GENMASK(0, 0); in rk3568_combphy_cfg()
526 val &= ~GENMASK(7, 6); in rk3568_combphy_cfg()
531 val &= ~GENMASK(7, 0); in rk3568_combphy_cfg()
561 val &= ~GENMASK(7, 4); in rk3568_combphy_cfg()
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/device/soc/rockchip/rk3588/kernel/drivers/net/ethernet/stmicro/stmmac/
Ddescs.h34 #define RDES0_FRAME_LEN_MASK GENMASK(29, 16)
39 #define RDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
40 #define RDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
52 #define ERDES1_BUFFER1_SIZE_MASK GENMASK(12, 0)
55 #define ERDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
64 #define TDES0_COLLISION_COUNT_MASK GENMASK(6, 3)
78 #define TDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
79 #define TDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
86 #define TDES1_CHECKSUM_INSERTION_MASK GENMASK(28, 27)
97 #define ETDES0_COLLISION_COUNT_MASK GENMASK(6, 3)
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Ddwmac1000.h90 #define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)
161 #define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20)
169 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
177 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
183 #define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */
191 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
/device/board/isoftstone/yangfan/kernel/src/driv/gpu/rockchip/
Drockchip-mipi-csi-tx.h27 #define m_LANE_NUM GENMASK(5, 4)
73 #define m_PIXEL_FORMAT GENMASK(7, 4)
74 #define m_VOP_DT_USERDEFINE GENMASK(13, 8)
75 #define m_VOP_VC_USERDEFINE GENMASK(15, 14)
76 #define m_VOP_WC_USERDEFINE GENMASK(31, 16)
88 #define m_VOP_LINE_PADDING_NUM GENMASK(7, 5)
90 #define m_VOP_WC_ACTIVE GENMASK(31, 16)
101 #define m_CAM_FORMAT GENMASK(7, 4)
102 #define m_BYPASS_DT_USERDEFINE GENMASK(13, 8)
103 #define m_BYPASS_VC_USERDEFINE GENMASK(15, 14)
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/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
Dphy-rockchip-inno-dsidphy.c25 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
42 #define LANE_EN_MASK GENMASK(6, 2)
48 #define POWER_WORK_MASK GENMASK(1, 0)
64 #define REG_PREDIV_MASK GENMASK(4, 0)
67 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
70 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
72 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)
75 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)
77 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)
80 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)
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/device/soc/rockchip/rk3588/kernel/include/linux/mfd/
Drk628.h19 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
20 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16))
27 #define SW_ADAPTER_I2CSLADR_MASK GENMASK(24, 22)
37 #define SW_OUTPUT_MODE_MASK GENMASK(7, 3)
39 #define SW_INPUT_MODE_MASK GENMASK(2, 0)
84 #define SW_TXPHY_REFCLK_SEL_MASK GENMASK(6, 5)
109 #define SW_HRES_MASK GENMASK(28, 16)
118 #define SW_SET_X_MASK GENMASK(28, 16)
120 #define SW_SET_Y_MASK GENMASK(28, 16)
136 #define FORCETXSTOPMODE_MASK GENMASK(19, 16)
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Drk630.h16 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
17 #define HIWORD_MASK(h, l) ((GENMASK((h), (l)) << 16) | GENMASK((h), (l)))
18 #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | (GENMASK((h), (l)) << 16))
81 #define VDAC_GAIN_MASK GENMASK(x, 5, 0)
/device/board/isoftstone/yangfan/kernel/src/driv/phy/
Dphy-rockchip-inno-mipi-dphy.c29 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
47 #define LANE_EN_MASK GENMASK(6, 2)
53 #define POWER_WORK_MASK GENMASK(1, 0)
69 #define REG_PREDIV_MASK GENMASK(4, 0)
72 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
75 #define CLK_LANE_SKEW_PHASE_SET_MASK GENMASK(2, 0)
80 #define LANE_3_SKEW_PHASE_SET_MASK GENMASK(6, 4)
84 #define LANE_2_SKEW_PHASE_SET_MASK GENMASK(2, 0)
89 #define LANE_1_SKEW_PHASE_SET_MASK GENMASK(6, 4)
93 #define LANE_0_SKEW_PHASE_SET_MASK GENMASK(2, 0)
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Dphy-rockchip-naneng-combphy.c100 mask = GENMASK(reg->bitend, reg->bitstart); in param_read()
112 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
123 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
337 (GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1])); in rockchip_combphy_parse_dt()
444 val &= ~GENMASK(5, 4); in rk3568_combphy_cfg()
456 val &= ~GENMASK(5, 4); in rk3568_combphy_cfg()
462 val &= ~GENMASK(0, 0); in rk3568_combphy_cfg()
526 val &= ~GENMASK(7, 6); in rk3568_combphy_cfg()
531 val &= ~GENMASK(7, 0); in rk3568_combphy_cfg()
561 val &= ~GENMASK(7, 4); in rk3568_combphy_cfg()
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/device/board/isoftstone/yangfan/kernel/src/incl/linux/phy/
Dphy-rockchip-usbdp.h25 #define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n))
26 #define DP_LANE_SEL_ALL GENMASK(7, 0)
34 #define CMN_DP_LANE_MUX_ALL GENMASK(7, 4)
35 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
40 #define CMN_DP_TX_LINK_BW GENMASK(6, 5)
/device/soc/rockchip/rk3588/kernel/include/linux/phy/
Dphy-rockchip-usbdp.h25 #define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n))
26 #define DP_LANE_SEL_ALL GENMASK(7, 0)
34 #define CMN_DP_LANE_MUX_ALL GENMASK(7, 4)
35 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
40 #define CMN_DP_TX_LINK_BW GENMASK(6, 5)
/device/soc/rockchip/common/sdk_linux/include/linux/usb/
Dtypec_tbt.h38 #define TBT_CABLE_SPEED(_vdo_) (((_vdo_)&GENMASK(18, 16)) >> 16)
42 #define TBT_CABLE_ROUNDED_SUPPORT(_vdo_) (((_vdo_)&GENMASK(20, 19)) >> 19)
49 #define TBT_SET_CABLE_SPEED(_s_) (((_s_)&GENMASK(2, 0)) << 16)
50 #define TBT_SET_CABLE_ROUNDED(_g_) (((_g_)&GENMASK(1, 0)) << 19)
/device/soc/amlogic/a311d/soc/amlogic/phy/
Dphy-meson-g12a-mipi-dphy-analog.c20 #define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(31, 16)
21 #define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
25 #define HHI_MIPI_CNTL2_DIF_REF_CTL2 GENMASK(15, 0)
28 #define HHI_MIPI_CNTL2_DIF_TX_CTL1 GENMASK(31, 16)
29 #define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
30 #define HHI_MIPI_CNTL2_DIF_TX_CTL0 GENMASK(10, 0)
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/net/wireless/xr829/umac/
Dsta_info.h810 #define STA_STATS_FIELD_HT_MCS GENMASK(7, 0)
811 #define STA_STATS_FIELD_LEGACY_IDX GENMASK(3, 0)
812 #define STA_STATS_FIELD_LEGACY_BAND GENMASK(7, 4)
813 #define STA_STATS_FIELD_VHT_MCS GENMASK(3, 0)
814 #define STA_STATS_FIELD_VHT_NSS GENMASK(7, 4)
815 #define STA_STATS_FIELD_HE_MCS GENMASK(3, 0)
816 #define STA_STATS_FIELD_HE_NSS GENMASK(7, 4)
817 #define STA_STATS_FIELD_BW GENMASK(11, 8)
818 #define STA_STATS_FIELD_SGI GENMASK(12, 12)
819 #define STA_STATS_FIELD_TYPE GENMASK(15, 13)
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/device/soc/rockchip/common/vendor/drivers/phy/
Dphy-rockchip-naneng-combphy.c100 mask = GENMASK(reg->bitend, reg->bitstart); in param_read()
111 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
122 mask = GENMASK(cfg->pipe_phy_status.bitend, cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
330 …regmap_write(priv->pipe_grf, vals[0], (GENMASK(vals[0x02], vals[1]) << 0x10) | (vals[0x03] << vals… in rockchip_combphy_parse_dt()
439 val &= ~GENMASK(0x05, 0x04); in rk3568_combphy_cfg()
451 val &= ~GENMASK(0x05, 0x04); in rk3568_combphy_cfg()
457 val &= ~GENMASK(0, 0); in rk3568_combphy_cfg()
521 val &= ~GENMASK(0x07, 0x06); in rk3568_combphy_cfg()
526 val &= ~GENMASK(0x07, 0); in rk3568_combphy_cfg()
556 val &= ~GENMASK(0x07, 0x04); in rk3568_combphy_cfg()
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/device/board/unionman/unionpi_tiger/kernel/hdf/audio/linux_drv/include/
Daxg_fifo.h45 #define FIFO_INT_MASK GENMASK(7, 0)
50 #define CTRL0_SEL_MASK GENMASK(2, 0)
54 #define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8)
57 #define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24)
/device/board/unionman/unionpi_tiger/kernel/hdf/audio/linux_drv/src/
Daxg_tdmout.c21 #define TDMOUT_CTRL0_BITNUM_MASK GENMASK(4, 0)
23 #define TDMOUT_CTRL0_SLOTNUM_MASK GENMASK(9, 5)
25 #define TDMOUT_CTRL0_INIT_BITNUM_MASK GENMASK(19, 15)
31 #define TDMOUT_CTRL1_TYPE_MASK GENMASK(6, 4)
34 #define TDMOUT_CTRL1_MSB_POS_MASK GENMASK(12, 8)
/device/soc/rockchip/common/sdk_linux/drivers/pci/controller/dwc/
Dpcie-designware.h34 #define PORT_AFR_N_FTS_MASK GENMASK(15, 8)
36 #define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16)
40 #define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
42 #define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
48 #define PORT_LINK_MODE_MASK GENMASK(21, 16)
63 #define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)
65 #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
101 #define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x)
102 #define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
103 #define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
/device/soc/rockchip/common/sdk_linux/drivers/nvmem/
Drockchip-otp.c36 #define OTPC_USER_ADDR_MASK GENMASK(31, 16)
38 #define OTPC_USE_USER_MASK GENMASK(16, 16)
40 #define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16)
46 #define SBPI_DAP_ADDR_MASK GENMASK(31, 24)
47 #define SBPI_CMD_VALID_MASK GENMASK(31, 16)
53 #define SBPI_ENABLE_MASK GENMASK(16, 16)
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/thermal/
Dsunxi_thermal.c20 #define FT_TEMP_MASK GENMASK(11, 0)
21 #define TEMP_CALIB_MASK GENMASK(11, 0)
31 #define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))
32 #define SUN50I_THS_CTRL0_FS_DIV(x) ((GENMASK(15, 0) & (x)) << 16)
34 #define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
35 #define SUN50I_H616_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)
284 val = GENMASK(tmdev->chip->sensor_num - 1, 0); in sun50i_h616_thermal_init()
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/ispp/
Dregs.h325 #define FMT_WR_MASK GENMASK(7, 4)
326 #define FMT_RD_MASK GENMASK(3, 0)
347 #define GLB_QUICK_MODE_MASK GENMASK(9, 8)
421 #define TNR_TILE_LINE_CNT_MASK GENMASK(6, 0)
422 #define NR_TILE_LINE_CNT_MASK GENMASK(14, 8)
423 #define FEC_TILE_LINE_CNT_MASK GENMASK(22, 16)
426 #define SW_TNR_WR_FORMAT_MASK GENMASK(7, 4)
427 #define SW_TNR_RD_FORMAT_MASK GENMASK(3, 0)
472 #define SW_SHP_WR_FORMAT_MASK GENMASK(3, 0)
516 #define SW_BIC_MODE GENMASK(4, 3)

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