| /third_party/cmsis/CMSIS/Core/Include/ |
| D | cachel1_armv7.h | 60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
197 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
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| D | core_starmc1.h | 540 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
3104 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
3111 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
3127 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
3192 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
3213 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
3235 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
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| D | core_cm0.h | 353 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm1.h | 353 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_sc000.h | 364 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm0plus.h | 371 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_sc300.h | 391 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm3.h | 391 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_armv8mbl.h | 399 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm23.h | 399 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm4.h | 464 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm7.h | 479 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| /third_party/cmsis/Device/ARM/ARMCM55/Source/ |
| D | system_ARMCM55.c | 94 SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; in SystemInit()
98 SCB->CCR |= SCB_CCR_LOB_Msk; in SystemInit()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBanks.td | 19 def CCRegBank : RegisterBank<"CC", [CCR]>;
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| D | AArch64GenRegisterBankInfo.def | 209 PMI_None, // CCR
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| D | AArch64RegisterInfo.td | 238 def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
241 // CCR is not allocatable.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 60 def CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> {
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenInstrInfo.inc | 14826 CCR = 297,
19286 OpTypes::GPR, OpTypes::GPR, OpTypes::imm0_32, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
19287 …ypes::GPRnopc, OpTypes::GPRnopc, OpTypes::GPRnopc, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
19325 OpTypes::GPR, OpTypes::GPR, OpTypes::imm0_31, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
19326 …ypes::GPRnopc, OpTypes::GPRnopc, OpTypes::GPRnopc, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
19327 OpTypes::GPR, OpTypes::GPR, OpTypes::imm0_32, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
19328 …ypes::GPRnopc, OpTypes::GPRnopc, OpTypes::GPRnopc, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
19330 …ypes::GPRnopc, OpTypes::GPRnopc, OpTypes::GPRnopc, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
19345 …ypes::GPRnopc, OpTypes::GPRnopc, OpTypes::GPRnopc, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
19368 OpTypes::GPR, OpTypes::GPR, OpTypes::imm0_31, OpTypes::i32imm, OpTypes::i32imm, OpTypes::CCR,
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4474 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local
4482 ARMcc, CCR, OverflowCmp); in LowerSignedALUO()
4594 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local
4597 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR, in LowerSELECT()
4629 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
4632 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG); in LowerSELECT()
4698 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV() argument
4712 ARMcc, CCR, Cmp); in getCMOV()
4714 ARMcc, CCR, duplicateCmp(Cmp, DAG)); in getCMOV()
4718 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, in getCMOV()
[all …]
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| D | ARMISelLowering.h | 818 SDValue ARMcc, SDValue CCR, SDValue Cmp,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 226 def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)>
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 421 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
654 def CCROpnd : RegisterOperand<CCR> {
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| /third_party/libunwind/src/ptrace/ |
| D | _UPT_reg_offset.c | 471 [UNW_PPC32_CCR] = UNW_PPC_PT(CCR)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 296 def CCR : RegisterClass<"SystemZ", [i32], 32, (add CC)>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 1925 // CCR Register Class...
1926 const MCPhysReg CCR[] = {
1930 // CCR Bit set.
2675 { CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 1, false },
3958 { 32, 32, 32, VTLists+0 }, // CCR
6239 { // CCR
7150 {0, 0}, // CCR
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