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Searched refs:ArgReg (Results 1 – 20 of 20) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/
DNios2ISelLowering.cpp111 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments() local
116 unsigned Reg = addLiveIn(MF, ArgReg, RC); in LowerFormalArguments()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp3136 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall() local
3148 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3149 ArgVT, ArgReg); in fastLowerCall()
3161 ArgReg = fastEmitZExtFromI1(MVT::i8, ArgReg, /*TODO: Kill=*/false); in fastLowerCall()
3164 if (ArgReg == 0) in fastLowerCall()
3168 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3169 ArgVT, ArgReg); in fastLowerCall()
3177 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3178 ArgVT, ArgReg); in fastLowerCall()
3180 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86FastISel.cpp3344 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall() local
3356 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3357 ArgVT, ArgReg); in fastLowerCall()
3369 ArgReg = fastEmitZExtFromI1(MVT::i8, ArgReg, /*TODO: Kill=*/false); in fastLowerCall()
3372 if (ArgReg == 0) in fastLowerCall()
3376 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3377 ArgVT, ArgReg); in fastLowerCall()
3385 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3386 ArgVT, ArgReg); in fastLowerCall()
3388 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
[all …]
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp1143 unsigned ArgReg = getRegForValue(ArgVal); in processCallArgs() local
1144 if (!ArgReg) in processCallArgs()
1155 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
1156 if (!ArgReg) in processCallArgs()
1163 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
1164 if (!ArgReg) in processCallArgs()
1175 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
DMipsISelLowering.cpp3081 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments() local
3086 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); in LowerFormalArguments()
3100 getNextIntArgReg(ArgReg), RC); in LowerFormalArguments()
3756 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs() local
3757 unsigned VReg = addLiveIn(MF, ArgReg, RC); in copyByValRegs()
3797 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() local
3798 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); in passByValArg()
3847 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() local
3848 RegsToPass.push_back(std::make_pair(ArgReg, Val)); in passByValArg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsFastISel.cpp1181 unsigned ArgReg = getRegForValue(ArgVal); in processCallArgs() local
1182 if (!ArgReg) in processCallArgs()
1193 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
1194 if (!ArgReg) in processCallArgs()
1201 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
1202 if (!ArgReg) in processCallArgs()
1213 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
DMipsISelLowering.cpp3375 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments() local
3380 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); in LowerFormalArguments()
3394 getNextIntArgReg(ArgReg), RC); in LowerFormalArguments()
4065 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs() local
4066 unsigned VReg = addLiveIn(MF, ArgReg, RC); in copyByValRegs()
4104 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() local
4105 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); in passByValArg()
4153 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() local
4154 RegsToPass.push_back(std::make_pair(ArgReg, Val)); in passByValArg()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FastISel.cpp1610 unsigned ArgReg; in DoSelectCall() local
1618 ArgReg = getRegForValue(ArgVal); in DoSelectCall()
1619 if (ArgReg == 0) return false; in DoSelectCall()
1624 ArgReg = FastEmit_ri(ArgVT, ArgVT, ISD::AND, ArgReg, in DoSelectCall()
1627 ArgReg = getRegForValue(ArgVal); in DoSelectCall()
1630 if (ArgReg == 0) return false; in DoSelectCall()
1641 Args.push_back(ArgReg); in DoSelectCall()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp494 unsigned ArgReg; in LowerReturn() local
496 ArgReg = Alpha::R0; in LowerReturn()
499 ArgReg = Alpha::F0; in LowerReturn()
501 Copy = DAG.getCopyToReg(Copy, dl, ArgReg, in LowerReturn()
504 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg); in LowerReturn()
/external/clang/lib/StaticAnalyzer/Core/
DBugReporterVisitors.cpp1665 const MemRegion *ArgReg = Call->getArgSVal(Idx).getAsRegion(); in VisitNode() local
1668 if ( !ArgReg || (ArgReg != R && !R->isSubRegionOf(ArgReg->StripCasts()))) in VisitNode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DThumb1FrameLowering.cpp776 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) in spillCalleeSavedRegisters()
777 if (!MF.getRegInfo().isLiveIn(ArgReg)) in spillCalleeSavedRegisters()
778 CopyRegs[ArgReg] = true; in spillCalleeSavedRegisters()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1375 unsigned ArgReg; in processCallArgs() local
1377 ArgReg = NextFPR++; in processCallArgs()
1381 ArgReg = NextGPR++; in processCallArgs()
1384 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg); in processCallArgs()
1385 RegArgs.push_back(ArgReg); in processCallArgs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1462 unsigned ArgReg; in processCallArgs() local
1464 ArgReg = NextFPR++; in processCallArgs()
1468 ArgReg = NextGPR++; in processCallArgs()
1471 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg); in processCallArgs()
1472 RegArgs.push_back(ArgReg); in processCallArgs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp3038 unsigned ArgReg = getRegForValue(ArgVal); in processCallArgs() local
3039 if (!ArgReg) in processCallArgs()
3049 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
3050 if (!ArgReg) in processCallArgs()
3059 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
3060 if (!ArgReg) in processCallArgs()
3071 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
3100 if (!emitStore(ArgVT, ArgReg, Addr, MMO)) in processCallArgs()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp2952 unsigned ArgReg = getRegForValue(ArgVal); in processCallArgs() local
2953 if (!ArgReg) in processCallArgs()
2963 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
2964 if (!ArgReg) in processCallArgs()
2973 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
2974 if (!ArgReg) in processCallArgs()
2985 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
3014 if (!emitStore(ArgVT, ArgReg, Addr, MMO)) in processCallArgs()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp708 for (unsigned ArgReg : Args) in selectCall() local
709 MIB.addReg(ArgReg); in selectCall()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp845 for (unsigned ArgReg : Args) in selectCall() local
846 MIB.addReg(ArgReg); in selectCall()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp2278 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments() local
2294 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); in LowerFormalArguments()
2318 getNextIntArgReg(ArgReg), RC); in LowerFormalArguments()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp90 unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg(); in parametersInCSRMatch() local
91 if (MRI.getLiveInPhysReg(ArgReg) != Reg) in parametersInCSRMatch()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp92 unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg(); in parametersInCSRMatch() local
93 if (MRI.getLiveInPhysReg(ArgReg) != Reg) in parametersInCSRMatch()