/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
D | CallLowering.cpp | 28 ArrayRef<unsigned> ArgRegs, std::function<unsigned()> GetCalleeReg) const { in lowerCall() argument 38 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{}, in lowerCall()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
D | ARCISelLowering.cpp | 522 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments() local 525 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCallArguments() 526 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCallArguments() 533 MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4, in LowerCallArguments() 537 for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) { in LowerCallArguments() 540 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCallArguments()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMFastISel.cpp | 193 SmallVectorImpl<unsigned> &ArgRegs, 1560 SmallVectorImpl<unsigned> &ArgRegs, in ProcessCallArgs() argument 1582 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs() 1815 SmallVector<unsigned, 8> ArgRegs; in ARMEmitLibcall() local 1819 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall() 1836 ArgRegs.push_back(Arg); in ARMEmitLibcall() 1844 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) in ARMEmitLibcall() 1913 SmallVector<unsigned, 8> ArgRegs; in SelectCall() local 1917 ArgRegs.reserve(CS.arg_size()); in SelectCall() 1948 ArgRegs.push_back(Arg); in SelectCall() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
D | CallLowering.h | 209 unsigned ResReg, ArrayRef<unsigned> ArgRegs,
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/external/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 192 SmallVectorImpl<unsigned> &ArgRegs, 1871 SmallVectorImpl<unsigned> &ArgRegs, in ProcessCallArgs() argument 1938 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs() 2209 SmallVector<unsigned, 8> ArgRegs; in ARMEmitLibcall() local 2213 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall() 2230 ArgRegs.push_back(Arg); in ARMEmitLibcall() 2238 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall() 2319 SmallVector<unsigned, 8> ArgRegs; in SelectCall() local 2324 ArgRegs.reserve(arg_size); in SelectCall() 2364 ArgRegs.push_back(Arg); in SelectCall() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 223 SmallVectorImpl<unsigned> &ArgRegs, 1897 SmallVectorImpl<unsigned> &ArgRegs, in ProcessCallArgs() argument 1964 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs() 2235 SmallVector<unsigned, 8> ArgRegs; in ARMEmitLibcall() local 2239 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall() 2255 ArgRegs.push_back(Arg); in ARMEmitLibcall() 2263 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall() 2344 SmallVector<unsigned, 8> ArgRegs; in SelectCall() local 2349 ArgRegs.reserve(arg_size); in SelectCall() 2389 ArgRegs.push_back(Arg); in SelectCall() [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 181 SmallVectorImpl<unsigned> &ArgRegs, 1278 SmallVectorImpl<unsigned> &ArgRegs, in processCallArgs() argument 1335 unsigned Arg = ArgRegs[VA.getValNo()]; in processCallArgs() 1509 SmallVector<unsigned, 8> ArgRegs; in fastLowerCall() local 1514 ArgRegs.reserve(NumArgs); in fastLowerCall() 1540 ArgRegs.push_back(Arg); in fastLowerCall() 1549 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
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D | PPCISelLowering.cpp | 2673 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local 2677 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() 2679 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() 2686 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs() 2700 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local 2705 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() 2707 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() 2711 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() 2712 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
D | RISCVISelLowering.cpp | 1032 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs); in LowerFormalArguments() local 1033 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments() 1046 if (ArgRegs.size() == Idx) { in LowerFormalArguments() 1050 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments() 1070 for (unsigned I = Idx; I < ArgRegs.size(); in LowerFormalArguments() 1073 RegInfo.addLiveIn(ArgRegs[I], Reg); in LowerFormalArguments()
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
D | XCoreISelLowering.cpp | 1146 static const unsigned ArgRegs[] = { in LowerCCCArguments() local 1150 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs, in LowerCCCArguments() 1151 array_lengthof(ArgRegs)); in LowerCCCArguments() 1152 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments() 1157 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments() 1168 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 182 SmallVectorImpl<unsigned> &ArgRegs, 1365 SmallVectorImpl<unsigned> &ArgRegs, in processCallArgs() argument 1422 unsigned Arg = ArgRegs[VA.getValNo()]; in processCallArgs() 1596 SmallVector<unsigned, 8> ArgRegs; in fastLowerCall() local 1601 ArgRegs.reserve(NumArgs); in fastLowerCall() 1627 ArgRegs.push_back(Arg); in fastLowerCall() 1636 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
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D | PPCISelLowering.cpp | 3131 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local 3135 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() 3137 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() 3144 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs() 3159 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local 3163 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() 3165 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() 3172 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() 3184 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local 3189 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
D | MBlazeISelLowering.cpp | 659 static const unsigned ArgRegs[] = { in CC_MBlaze_AssignReg() local 664 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_MBlaze_AssignReg() 665 unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs); in CC_MBlaze_AssignReg()
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 305 static const unsigned ArgRegs[] = { in LowerFormalArguments() local 308 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); in LowerFormalArguments() 309 const unsigned *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.cpp | 1340 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local 1344 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments() 1345 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments() 1349 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments() 1359 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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/external/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.cpp | 1357 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local 1361 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments() 1362 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments() 1366 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments() 1376 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 3785 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local 3797 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() 3847 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() 3871 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in writeVarArgRegs() local 3872 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs() 3883 if (ArgRegs.size() == Idx) in writeVarArgRegs() 3888 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs() 3900 for (unsigned I = Idx; I < ArgRegs.size(); in writeVarArgRegs() 3902 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 4093 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local 4104 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() 4153 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() 4177 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in writeVarArgRegs() local 4178 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs() 4189 if (ArgRegs.size() == Idx) in writeVarArgRegs() 4194 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs() 4206 for (unsigned I = Idx; I < ArgRegs.size(); in writeVarArgRegs() 4208 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 1533 static const unsigned ArgRegs[] = { in CC_PPC_SVR4_Custom_AlignArgRegs() local 1537 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC_SVR4_Custom_AlignArgRegs() 1539 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignArgRegs() 1546 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignArgRegs() 1560 static const unsigned ArgRegs[] = { in CC_PPC_SVR4_Custom_AlignFPArgRegs() local 1565 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC_SVR4_Custom_AlignFPArgRegs() 1567 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignFPArgRegs() 1571 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC_SVR4_Custom_AlignFPArgRegs() 1572 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignFPArgRegs()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 134 static const MCPhysReg ArgRegs[] = { in CC_SkipOdd() local 138 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_SkipOdd() 139 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_SkipOdd() 143 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 542 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local 545 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments_32() 546 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments_32()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 536 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local 539 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments_32() 540 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments_32()
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/external/llvm/lib/Target/X86/ |
D | X86FastISel.cpp | 3059 SmallVector<unsigned, 16> ArgRegs; in fastLowerCall() local 3104 ArgRegs.push_back(ResultReg); in fastLowerCall() 3136 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86FastISel.cpp | 3267 SmallVector<unsigned, 16> ArgRegs; in fastLowerCall() local 3312 ArgRegs.push_back(ResultReg); in fastLowerCall() 3344 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall()
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
D | SPUISelLowering.cpp | 1201 static const unsigned ArgRegs[] = { in LowerFormalArguments() local 1225 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass); in LowerFormalArguments()
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