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/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/bidi/
DTestClassOverride.java28 private static final int DEF = TestData.DEF; field in TestClassOverride
46 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //00-07
47 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //08-0F
48 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //10-17
49 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //18-1F
50 DEF, DEF, DEF, DEF, DEF, DEF, R, DEF, //20-27
51 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //28-2F
53 AN, AN, DEF, DEF, DEF, DEF, DEF, DEF, //38-3F
57 R, R, R, LRE, DEF, RLE, PDF, S, //58-5F
58 NSM, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //60-67
[all …]
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/bidi/
DTestClassOverride.java25 private static final int DEF = TestData.DEF; field in TestClassOverride
43 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //00-07
44 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //08-0F
45 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //10-17
46 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //18-1F
47 DEF, DEF, DEF, DEF, DEF, DEF, R, DEF, //20-27
48 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //28-2F
50 AN, AN, DEF, DEF, DEF, DEF, DEF, DEF, //38-3F
54 R, R, R, LRE, DEF, RLE, PDF, S, //58-5F
55 NSM, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //60-67
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dlegalize-memop-scalar.mir36 ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
37 ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
38 ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
39 ; X64: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
40 ; X64: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
41 ; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 8)
45 ; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
46 ; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
47 ; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
48 ; X64: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
[all …]
Dlegalize-undef.mir13 ; X64: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
15 ; X64: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store 1)
17 ; X64: G_STORE [[DEF2]](s8), [[DEF]](p0) :: (store 1)
19 ; X64: G_STORE [[DEF3]](s16), [[DEF]](p0) :: (store 2)
21 ; X64: G_STORE [[DEF4]](s32), [[DEF]](p0) :: (store 4)
23 ; X64: G_STORE [[DEF5]](s64), [[DEF]](p0) :: (store 8)
25 ; X32: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
27 ; X32: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store 1)
29 ; X32: G_STORE [[DEF2]](s8), [[DEF]](p0) :: (store 1)
31 ; X32: G_STORE [[DEF3]](s16), [[DEF]](p0) :: (store 2)
[all …]
Dlegalize-or-scalar.mir48 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
52 ; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
76 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
77 ; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[DEF]], [[DEF]]
101 ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
102 ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[DEF]], [[DEF]]
126 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
127 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[DEF]]
151 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
152 ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
Dlegalize-gep.mir35 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
38 ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[SEXT]](s32)
39 ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
57 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
60 ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[SEXT]](s32)
61 ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
79 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
81 ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
82 ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
100 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
[all …]
Dlegalize-xor-scalar.mir71 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
72 ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[DEF]], [[DEF]]
96 ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
97 ; CHECK: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[DEF]], [[DEF]]
121 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
122 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[DEF]]
146 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
147 ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
Dlegalize-and-scalar.mir73 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
74 ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[DEF]], [[DEF]]
98 ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
99 ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[DEF]], [[DEF]]
123 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
124 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[DEF]]
148 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
149 ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
Dselect-merge-vec512.mir25 ; ALL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
26 ; ALL: undef %2.sub_xmm:vr512 = COPY [[DEF]]
27 ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr %2, [[DEF]], 1
28 ; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2
29 ; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3
50 ; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
51 ; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]]
52 ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr %2, [[DEF]], 1
Dselect-unmerge-vec512.mir28 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
29 ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm
30 ; ALL: [[VEXTRACTF32x4Zrr:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 1
31 ; ALL: [[VEXTRACTF32x4Zrr1:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 2
32 ; ALL: [[VEXTRACTF32x4Zrr2:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 3
54 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
55 ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY [[DEF]].sub_ymm
56 ; ALL: [[VEXTRACTF64x4Zrr:%[0-9]+]]:vr256x = VEXTRACTF64x4Zrr [[DEF]], 1
Dlegalize-trunc.mir20 ; X32: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
23 ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
26 ; X32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
28 ; X32: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
32 ; X64: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
35 ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
38 ; X64: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
40 ; X64: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
Dlegalize-add-v256.mir42 ; ALL: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
44 …; SSE2: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x…
46 …; AVX1: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x…
56 ; AVX2: [[ADD:%[0-9]+]]:_(<32 x s8>) = G_ADD [[DEF]], [[DEF1]]
80 ; ALL: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
82 …; SSE2: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x…
87 …; AVX1: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x…
94 ; AVX2: [[ADD:%[0-9]+]]:_(<16 x s16>) = G_ADD [[DEF]], [[DEF1]]
118 ; ALL: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
120 …; SSE2: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x …
[all …]
Dselect-merge-vec256.mir24 ; AVX: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
25 ; AVX: undef %2.sub_xmm:vr256 = COPY [[DEF]]
26 ; AVX: [[VINSERTF128rr:%[0-9]+]]:vr256 = VINSERTF128rr %2, [[DEF]], 1
30 ; AVX512VL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
31 ; AVX512VL: undef %2.sub_xmm:vr256x = COPY [[DEF]]
32 ; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]]:vr256x = VINSERTF32x4Z256rr %2, [[DEF]], 1
Dselect-unmerge-vec256.mir26 ; AVX: [[DEF:%[0-9]+]]:vr256 = IMPLICIT_DEF
27 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY [[DEF]].sub_xmm
28 ; AVX: [[VEXTRACTF128rr:%[0-9]+]]:vr128 = VEXTRACTF128rr [[DEF]], 1
33 ; AVX512VL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
34 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm
35 ; AVX512VL: [[VEXTRACTF32x4Z256rr:%[0-9]+]]:vr128x = VEXTRACTF32x4Z256rr [[DEF]], 1
Dlegalize-sub-v128.mir39 ; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
41 ; ALL: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
64 ; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
66 ; ALL: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
89 ; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
91 ; ALL: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
114 ; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
116 ; ALL: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
Dlegalize-sub-v512.mir40 ; ALL: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
42 ; ALL: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[DEF]], [[DEF1]]
65 ; ALL: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
67 ; ALL: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[DEF]], [[DEF1]]
90 ; ALL: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
92 ; ALL: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
115 ; ALL: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
117 ; ALL: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
Dlegalize-sub-v256.mir40 ; ALL: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
42 ; ALL: [[SUB:%[0-9]+]]:_(<32 x s8>) = G_SUB [[DEF]], [[DEF1]]
65 ; ALL: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
67 ; ALL: [[SUB:%[0-9]+]]:_(<16 x s16>) = G_SUB [[DEF]], [[DEF1]]
90 ; ALL: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
92 ; ALL: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[DEF]], [[DEF1]]
115 ; ALL: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
117 ; ALL: [[SUB:%[0-9]+]]:_(<4 x s64>) = G_SUB [[DEF]], [[DEF1]]
Dlegalize-add-v128.mir39 ; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
41 ; ALL: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]]
65 ; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
67 ; ALL: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]]
91 ; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
93 ; ALL: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]]
117 ; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
119 ; ALL: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]]
Dselect-undef.mir32 ; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
33 ; ALL: $al = COPY [[DEF]]
59 ; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
60 ; ALL: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[DEF]], implicit-def $eflags
81 ; ALL: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
82 ; ALL: $xmm0 = COPY [[DEF]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/
Drangereduce.ll12 ; CHECK-NEXT: switch i32 [[TMP4]], label [[DEF:%.*]] [
22 ; CHECK-NEXT: br label [[DEF]]
24 ; CHECK-NEXT: br label [[DEF]]
26 ; CHECK-NEXT: br label [[DEF]]
49 ; CHECK-NEXT: switch i128 [[A:%.*]], label [[DEF:%.*]] [
59 ; CHECK-NEXT: br label [[DEF]]
61 ; CHECK-NEXT: br label [[DEF]]
63 ; CHECK-NEXT: br label [[DEF]]
86 ; CHECK-NEXT: switch i32 [[A:%.*]], label [[DEF:%.*]] [
95 ; CHECK-NEXT: br label [[DEF]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-implicit-def.mir15 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
16 ; GCN: FLAT_STORE_DWORD [[COPY]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr
32 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
33 ; GCN: FLAT_STORE_DWORDX2 [[COPY]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr
61 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
63 ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
77 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
79 ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
93 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
95 ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
/external/llvm/test/MC/AsmParser/
Dmacro_parsing.s3 .macro DEF num macro
6 DEF 02
7 DEF 08
8 DEF 09
9 DEF 0A
10 DEF 10
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AsmParser/
Dmacro_parsing.s3 .macro DEF num macro
6 DEF 02
7 DEF 08
8 DEF 09
9 DEF 0A
10 DEF 10
/external/libusb/msvc/
Dlibusb_wince.sln8 Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "xusb", "xusb_wince.vcproj", "{93F53A7E-6DEF-46…
116 …{93F53A7E-6DEF-469A-ABD4-A5AD02A0A511}.Debug|STANDARDSDK_500 (ARMV4I).ActiveCfg = Debug|STANDARDSD…
117 …{93F53A7E-6DEF-469A-ABD4-A5AD02A0A511}.Debug|STANDARDSDK_500 (ARMV4I).Build.0 = Debug|STANDARDSDK_…
118 …{93F53A7E-6DEF-469A-ABD4-A5AD02A0A511}.Debug|STANDARDSDK_500 (ARMV4I).Deploy.0 = Debug|STANDARDSDK…
119 …{93F53A7E-6DEF-469A-ABD4-A5AD02A0A511}.Debug|STANDARDSDK_500 (MIPSII).ActiveCfg = Debug|STANDARDSD…
120 …{93F53A7E-6DEF-469A-ABD4-A5AD02A0A511}.Debug|STANDARDSDK_500 (MIPSII).Build.0 = Debug|STANDARDSDK_…
121 …{93F53A7E-6DEF-469A-ABD4-A5AD02A0A511}.Debug|STANDARDSDK_500 (MIPSII).Deploy.0 = Debug|STANDARDSDK…
122 …{93F53A7E-6DEF-469A-ABD4-A5AD02A0A511}.Debug|STANDARDSDK_500 (MIPSII_FP).ActiveCfg = Debug|STANDAR…
123 …{93F53A7E-6DEF-469A-ABD4-A5AD02A0A511}.Debug|STANDARDSDK_500 (MIPSII_FP).Build.0 = Debug|STANDARDS…
124 …{93F53A7E-6DEF-469A-ABD4-A5AD02A0A511}.Debug|STANDARDSDK_500 (MIPSII_FP).Deploy.0 = Debug|STANDARD…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-implicit-def.mir22 ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
23 ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[DEF]], [[DEF]]
40 ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
41 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY [[DEF]]

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