| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 26 static SDValue emitMemMem(SelectionDAG &DAG, const SDLoc &DL, unsigned Sequence, in emitMemMem() argument
42 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
43 DAG.getConstant(Size, DL, PtrVT), in emitMemMem()
44 DAG.getConstant(Size / 256, DL, PtrVT)); in emitMemMem()
45 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
46 DAG.getConstant(Size, DL, PtrVT)); in emitMemMem()
50 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, in EmitTargetCodeForMemcpy() argument
57 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, in EmitTargetCodeForMemcpy()
65 static SDValue memsetStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, in memsetStore() argument
72 Chain, DL, DAG.getConstant(StoreVal, DL, MVT::getIntegerVT(Size * 8)), in memsetStore()
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| D | SystemZISelLowering.cpp | 548 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType() argument
698 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
1033 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL, in convertLocVTToValVT() argument
1039 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1042 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1046 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1052 Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)}); in convertLocVTToValVT()
1053 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1062 static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL, in convertValVTToLocVT() argument
1066 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 26 static SDValue emitMemMem(SelectionDAG &DAG, const SDLoc &DL, unsigned Sequence, in emitMemMem() argument
42 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
43 DAG.getConstant(Size, DL, PtrVT), in emitMemMem()
44 DAG.getConstant(Size / 256, DL, PtrVT)); in emitMemMem()
45 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
46 DAG.getConstant(Size, DL, PtrVT)); in emitMemMem()
50 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, in EmitTargetCodeForMemcpy() argument
57 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, in EmitTargetCodeForMemcpy()
65 static SDValue memsetStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, in memsetStore() argument
71 return DAG.getStore(Chain, DL, in memsetStore()
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| D | SystemZISelLowering.cpp | 465 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType() argument
518 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
809 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL, in convertLocVTToValVT() argument
815 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
818 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
822 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
828 Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)}); in convertLocVTToValVT()
829 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
838 static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL, in convertValVTToLocVT() argument
842 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Utils/ |
| D | VNCoercion.cpp | 16 const DataLayout &DL) { in canCoerceMustAliasedValueToLoad() argument
23 uint64_t StoreSize = DL.getTypeSizeInBits(StoredVal->getType()); in canCoerceMustAliasedValueToLoad()
30 if (StoreSize < DL.getTypeSizeInBits(LoadTy)) in canCoerceMustAliasedValueToLoad()
34 if (DL.isNonIntegralPointerType(StoredVal->getType()) != in canCoerceMustAliasedValueToLoad()
35 DL.isNonIntegralPointerType(LoadTy)) in canCoerceMustAliasedValueToLoad()
44 const DataLayout &DL) { in coerceAvailableValueToLoadTypeHelper() argument
45 assert(canCoerceMustAliasedValueToLoad(StoredVal, LoadedTy, DL) && in coerceAvailableValueToLoadTypeHelper()
48 if (auto *FoldedStoredVal = ConstantFoldConstant(C, DL)) in coerceAvailableValueToLoadTypeHelper()
54 uint64_t StoredValSize = DL.getTypeSizeInBits(StoredValTy); in coerceAvailableValueToLoadTypeHelper()
55 uint64_t LoadedValSize = DL.getTypeSizeInBits(LoadedTy); in coerceAvailableValueToLoadTypeHelper()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | Loads.cpp | 29 const DataLayout &DL) { in isAligned() argument
30 APInt BaseAlign(Offset.getBitWidth(), Base->getPointerAlignment(DL)); in isAligned()
36 BaseAlign = DL.getABITypeAlignment(Ty); in isAligned()
45 static bool isAligned(const Value *Base, unsigned Align, const DataLayout &DL) { in isAligned() argument
48 APInt Offset(DL.getTypeStoreSizeInBits(Ty), 0); in isAligned()
49 return isAligned(Base, Offset, Align, DL); in isAligned()
55 const Value *V, unsigned Align, const APInt &Size, const DataLayout &DL, in isDereferenceableAndAlignedPointer() argument
68 DL, CtxI, DT, Visited); in isDereferenceableAndAlignedPointer()
72 V->getPointerDereferenceableBytes(DL, CheckForNonNull)); in isDereferenceableAndAlignedPointer()
75 if (!CheckForNonNull || isKnownNonZero(V, DL, 0, nullptr, CtxI, DT)) in isDereferenceableAndAlignedPointer()
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| /external/llvm/lib/Analysis/ |
| D | Loads.cpp | 29 const DataLayout &DL) { in isAligned() argument
30 APInt BaseAlign(Offset.getBitWidth(), Base->getPointerAlignment(DL)); in isAligned()
36 BaseAlign = DL.getABITypeAlignment(Ty); in isAligned()
45 static bool isAligned(const Value *Base, unsigned Align, const DataLayout &DL) { in isAligned() argument
48 APInt Offset(DL.getTypeStoreSizeInBits(Ty), 0); in isAligned()
49 return isAligned(Base, Offset, Align, DL); in isAligned()
55 const Value *V, unsigned Align, const APInt &Size, const DataLayout &DL, in isDereferenceableAndAlignedPointer() argument
64 DL, CtxI, DT, Visited); in isDereferenceableAndAlignedPointer()
68 V->getPointerDereferenceableBytes(DL, CheckForNonNull)); in isDereferenceableAndAlignedPointer()
72 return isAligned(V, Align, DL); in isDereferenceableAndAlignedPointer()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 506 SDLoc DL(Op); in LowerOperation() local
512 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
513 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
514 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
515 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
517 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
530 SDLoc DL(Op); in LowerOperation() local
547 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
549 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
550 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
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| /external/llvm/lib/IR/ |
| D | Mangler.cpp | 34 const DataLayout &DL, char Prefix) { in getNameWithPrefixImpl() argument
47 OS << DL.getPrivateGlobalPrefix(); in getNameWithPrefixImpl()
49 OS << DL.getLinkerPrivateGlobalPrefix(); in getNameWithPrefixImpl()
59 const DataLayout &DL, in getNameWithPrefixImpl() argument
61 char Prefix = DL.getGlobalPrefix(); in getNameWithPrefixImpl()
62 return getNameWithPrefixImpl(OS, GVName, PrefixTy, DL, Prefix); in getNameWithPrefixImpl()
66 const DataLayout &DL) { in getNameWithPrefix() argument
67 return getNameWithPrefixImpl(OS, GVName, DL, Default); in getNameWithPrefix()
71 const Twine &GVName, const DataLayout &DL) { in getNameWithPrefix() argument
73 char Prefix = DL.getGlobalPrefix(); in getNameWithPrefix()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 645 SDLoc DL(Op); in LowerOperation() local
651 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
652 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
653 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
654 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
656 return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
669 SDLoc DL(Op); in LowerOperation() local
719 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
721 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
722 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 196 DebugLoc DL, in LowerFPToInt() argument
258 BuildMI(BB, DL, TII.get(Abs), Tmp0) in LowerFPToInt()
261 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
263 BuildMI(BB, DL, TII.get(LT), CmpReg) in LowerFPToInt()
272 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
274 BuildMI(BB, DL, TII.get(GE), SecondCmpReg) in LowerFPToInt()
277 BuildMI(BB, DL, TII.get(And), AndReg) in LowerFPToInt()
283 BuildMI(BB, DL, TII.get(Eqz), EqzReg) in LowerFPToInt()
288 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)) in LowerFPToInt()
291 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg) in LowerFPToInt()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
| D | Mangler.cpp | 35 const DataLayout &DL, char Prefix) { in getNameWithPrefixImpl() argument
47 if (DL.doNotMangleLeadingQuestionMark() && Name[0] == '?') in getNameWithPrefixImpl()
51 OS << DL.getPrivateGlobalPrefix(); in getNameWithPrefixImpl()
53 OS << DL.getLinkerPrivateGlobalPrefix(); in getNameWithPrefixImpl()
63 const DataLayout &DL, in getNameWithPrefixImpl() argument
65 char Prefix = DL.getGlobalPrefix(); in getNameWithPrefixImpl()
66 return getNameWithPrefixImpl(OS, GVName, PrefixTy, DL, Prefix); in getNameWithPrefixImpl()
70 const DataLayout &DL) { in getNameWithPrefix() argument
71 return getNameWithPrefixImpl(OS, GVName, DL, Default); in getNameWithPrefix()
75 const Twine &GVName, const DataLayout &DL) { in getNameWithPrefix() argument
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 218 bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
260 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *msg) { in fail() argument
263 DiagnosticInfoUnsupported(*MF.getFunction(), msg, DL.getDebugLoc())); in fail()
282 SDLoc DL = CLI.DL; in LowerCall() local
290 fail(DL, DAG, in LowerCall()
294 fail(DL, DAG, "WebAssembly doesn't support patch point yet"); in LowerCall()
301 fail(DL, DAG, "WebAssembly doesn't support tail call yet"); in LowerCall()
306 fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet"); in LowerCall()
314 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments"); in LowerCall()
316 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments"); in LowerCall()
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| /external/swiftshader/third_party/llvm-7.0/llvm/bindings/ocaml/target/ |
| D | target_ocaml.c | 69 CAMLprim value llvm_datalayout_byte_order(value DL) { in llvm_datalayout_byte_order() argument
70 return Val_int(LLVMByteOrder(DataLayout_val(DL))); in llvm_datalayout_byte_order()
74 CAMLprim value llvm_datalayout_pointer_size(value DL) { in llvm_datalayout_pointer_size() argument
75 return Val_int(LLVMPointerSize(DataLayout_val(DL))); in llvm_datalayout_pointer_size()
79 CAMLprim LLVMTypeRef llvm_datalayout_intptr_type(LLVMContextRef C, value DL) { in llvm_datalayout_intptr_type() argument
80 return LLVMIntPtrTypeInContext(C, DataLayout_val(DL)); in llvm_datalayout_intptr_type()
84 CAMLprim value llvm_datalayout_qualified_pointer_size(value AS, value DL) { in llvm_datalayout_qualified_pointer_size() argument
85 return Val_int(LLVMPointerSizeForAS(DataLayout_val(DL), Int_val(AS))); in llvm_datalayout_qualified_pointer_size()
91 value DL) { in llvm_datalayout_qualified_intptr_type() argument
92 return LLVMIntPtrTypeForASInContext(C, DataLayout_val(DL), Int_val(AS)); in llvm_datalayout_qualified_intptr_type()
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| /external/llvm/bindings/ocaml/target/ |
| D | target_ocaml.c | 69 CAMLprim value llvm_datalayout_byte_order(value DL) { in llvm_datalayout_byte_order() argument
70 return Val_int(LLVMByteOrder(DataLayout_val(DL))); in llvm_datalayout_byte_order()
74 CAMLprim value llvm_datalayout_pointer_size(value DL) { in llvm_datalayout_pointer_size() argument
75 return Val_int(LLVMPointerSize(DataLayout_val(DL))); in llvm_datalayout_pointer_size()
79 CAMLprim LLVMTypeRef llvm_datalayout_intptr_type(LLVMContextRef C, value DL) { in llvm_datalayout_intptr_type() argument
80 return LLVMIntPtrTypeInContext(C, DataLayout_val(DL));; in llvm_datalayout_intptr_type()
84 CAMLprim value llvm_datalayout_qualified_pointer_size(value AS, value DL) { in llvm_datalayout_qualified_pointer_size() argument
85 return Val_int(LLVMPointerSizeForAS(DataLayout_val(DL), Int_val(AS))); in llvm_datalayout_qualified_pointer_size()
91 value DL) { in llvm_datalayout_qualified_intptr_type() argument
92 return LLVMIntPtrTypeForASInContext(C, DataLayout_val(DL), Int_val(AS)); in llvm_datalayout_qualified_intptr_type()
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| /external/llvm/include/llvm/Analysis/ |
| D | InstructionSimplify.h | 52 const DataLayout &DL,
61 const DataLayout &DL,
70 const DataLayout &DL,
79 const DataLayout &DL,
88 const DataLayout &DL,
96 Value *SimplifyMulInst(Value *LHS, Value *RHS, const DataLayout &DL,
104 Value *SimplifySDivInst(Value *LHS, Value *RHS, const DataLayout &DL,
112 Value *SimplifyUDivInst(Value *LHS, Value *RHS, const DataLayout &DL,
121 const DataLayout &DL,
129 Value *SimplifySRemInst(Value *LHS, Value *RHS, const DataLayout &DL,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 477 SDLoc DL(N); in performDivRemCombine() local
479 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, in performDivRemCombine()
486 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, in performDivRemCombine()
495 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, in performDivRemCombine()
555 SDLoc DL(Op); in createFPCmp() local
561 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, in createFPCmp()
562 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); in createFPCmp()
567 SDValue False, const SDLoc &DL) { in createCMovFP() argument
572 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, in createCMovFP()
606 const SDLoc DL(N); in performSELECTCombine() local
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| D | MipsSEISelLowering.cpp | 428 SDLoc DL(ADDENode); in selectMADD() local
431 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, in selectMADD()
438 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, in selectMADD()
445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in selectMADD()
449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); in selectMADD()
500 SDLoc DL(SUBENode); in selectMSUB() local
503 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, in selectMSUB()
510 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue, in selectMSUB()
517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); in selectMSUB()
521 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); in selectMSUB()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 408 SDLoc DL(Op); in lowerSELECT() local
413 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
414 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
784 static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, in genConstMult() argument
788 return DAG.getConstant(0, DL, VT); in genConstMult()
796 return DAG.getNode(ISD::SHL, DL, VT, X, in genConstMult()
797 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult()
808 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
809 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
810 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); in genConstMult()
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| D | MipsISelLowering.cpp | 573 SDLoc DL(N); in performDivRemCombine() local
575 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, in performDivRemCombine()
582 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, in performDivRemCombine()
591 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, in performDivRemCombine()
650 SDLoc DL(Op); in createFPCmp() local
656 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, in createFPCmp()
657 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); in createFPCmp()
662 SDValue False, const SDLoc &DL) { in createCMovFP() argument
667 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, in createCMovFP()
701 const SDLoc DL(N); in performSELECTCombine() local
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| D | MipsSEISelDAGToDAG.cpp | 148 DebugLoc DL; in initGlobalBaseReg() local
165 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
167 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
169 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1) in initGlobalBaseReg()
179 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
181 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
194 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
196 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
197 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) in initGlobalBaseReg()
223 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg) in initGlobalBaseReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | ShadowCallStack.cpp | 67 MachineBasicBlock &MBB, const DebugLoc &DL);
69 MachineBasicBlock &MBB, const DebugLoc &DL,
90 MachineBasicBlock &MBB, const DebugLoc &DL) { in addProlog() argument
96 addDirectMem(BuildMI(MBB, MBBI, DL, TII->get(X86::MOV64rm)).addDef(ReturnReg), in addProlog()
99 BuildMI(MBB, MBBI, DL, TII->get(X86::XOR64rr)) in addProlog()
104 addSegmentedMem(BuildMI(MBB, MBBI, DL, TII->get(X86::ADD64mi8)), X86::GS, in addProlog()
109 BuildMI(MBB, MBBI, DL, TII->get(X86::MOV64rm)).addDef(OffsetReg), X86::GS, in addProlog()
112 addSegmentedMem(BuildMI(MBB, MBBI, DL, TII->get(X86::MOV64mr)), X86::GS, in addProlog()
118 MachineBasicBlock &MBB, const DebugLoc &DL, in addPrologLeaf() argument
121 addDirectMem(BuildMI(MBB, MBB.begin(), DL, TII->get(X86::MOV64rm)) in addPrologLeaf()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 382 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
387 return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals); in LowerFormalArguments()
396 SDLoc &DL = CLI.DL; in LowerCall() local
413 OutVals, Ins, DL, DAG, InVals); in LowerCall()
423 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCCCArguments() argument
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
455 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
458 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
462 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerCCCArguments()
489 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 36 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg) { in fail() argument
39 DiagnosticInfoUnsupported(*MF.getFunction(), Msg, DL.getDebugLoc())); in fail()
42 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg, in fail() argument
51 DiagnosticInfoUnsupported(*MF.getFunction(), Str, DL.getDebugLoc())); in fail()
153 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
184 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
190 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
193 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
197 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
202 fail(DL, DAG, "defined with too many args"); in LowerFormalArguments()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Analysis/ |
| D | ValueTracking.h | 54 const DataLayout &DL, unsigned Depth = 0,
61 KnownBits computeKnownBits(const Value *V, const DataLayout &DL,
75 const DataLayout &DL,
85 bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL,
99 bool isKnownNonZero(const Value *V, const DataLayout &DL, unsigned Depth = 0,
111 bool isKnownNonNegative(const Value *V, const DataLayout &DL,
119 bool isKnownPositive(const Value *V, const DataLayout &DL, unsigned Depth = 0,
126 bool isKnownNegative(const Value *V, const DataLayout &DL, unsigned Depth = 0,
133 bool isKnownNonEqual(const Value *V1, const Value *V2, const DataLayout &DL,
148 const DataLayout &DL,
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