/external/capstone/arch/XCore/ |
D | XCoreDisassembler.c | 192 static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) in Decode2OpInstruction() argument 210 *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2); in Decode2OpInstruction() 216 unsigned *Op1, unsigned *Op2, unsigned *Op3) in Decode3OpInstruction() argument 227 *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2); in Decode3OpInstruction() 309 unsigned Op1, Op2; in Decode2RInstruction() local 310 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction() 315 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction() 323 unsigned Op1, Op2; in Decode2RImmInstruction() local 324 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RImmInstruction() 329 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction() [all …]
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/external/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiMCCodeEmitter.cpp | 145 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local 148 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits() 149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits() 156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits() 157 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits() 193 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local 197 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue() 203 if (Op2.isImm()) { in getRiMemoryOpValue() 204 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue() 207 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiMCCodeEmitter.cpp | 143 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local 146 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits() 147 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits() 154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits() 155 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits() 191 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local 195 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue() 201 if (Op2.isImm()) { in getRiMemoryOpValue() 202 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue() 205 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue() [all …]
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/external/llvm/lib/Target/XCore/Disassembler/ |
D | XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument 254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction() 259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument 269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction() 347 unsigned Op1, Op2; in Decode2RInstruction() local 348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction() 353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction() 360 unsigned Op1, Op2; in Decode2RImmInstruction() local 361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction() 366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/Disassembler/ |
D | XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument 254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction() 259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument 269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction() 347 unsigned Op1, Op2; in Decode2RInstruction() local 348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction() 353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction() 360 unsigned Op1, Op2; in Decode2RImmInstruction() local 361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction() 366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction() [all …]
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/external/swiftshader/third_party/subzero/pnacl-llvm/include/llvm/Bitcode/NaCl/ |
D | NaClBitCodes.h | 225 const NaClBitCodeAbbrevOp &Op2) { 226 return Op1.Compare(Op2) < 0; 230 const NaClBitCodeAbbrevOp &Op2) { 231 return Op1.Compare(Op2) <= 0; 235 const NaClBitCodeAbbrevOp &Op2) { 236 return Op1.Compare(Op2) == 0; 240 const NaClBitCodeAbbrevOp &Op2) { 241 return Op1.Compare(Op2) != 0; 245 const NaClBitCodeAbbrevOp &Op2) { 246 return Op1.Compare(Op2) >= 0; [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument 171 if (Op1.getType() != Op2.getType()) in isSameOperand() 176 return Op1.getReg() == Op2.getReg(); in isSameOperand() 178 return Op1.getImm() == Op2.getImm(); in isSameOperand() 295 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local 302 if (Op2.isImm()) { in isSuitableAluInstr() 315 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr() 316 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr() 317 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr() 319 } else if (Op2.isReg()) { in isSuitableAluInstr() [all …]
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/external/llvm/lib/Target/Lanai/ |
D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument 171 if (Op1.getType() != Op2.getType()) in isSameOperand() 176 return Op1.getReg() == Op2.getReg(); in isSameOperand() 178 return Op1.getImm() == Op2.getImm(); in isSameOperand() 295 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local 302 if (Op2.isImm()) { in isSuitableAluInstr() 315 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr() 316 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr() 317 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr() 319 } else if (Op2.isReg()) { in isSuitableAluInstr() [all …]
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/external/v8/tools/clang/rewrite_to_chrome_style/tests/ |
D | operators-original.cc | 11 struct Op2 {}; struct 13 inline bool operator==(const Op2&, const Op2) { in operator ==() argument 23 blink::Op2 a2, b2; in G()
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D | operators-expected.cc | 11 struct Op2 {}; struct 13 inline bool operator==(const Op2&, const Op2) { in operator ==() argument 23 blink::Op2 a2, b2; in G()
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/external/llvm/lib/Target/AArch64/Utils/ |
D | AArch64BaseInfo.cpp | 93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local 99 Ops[5].getAsInteger(10, Op2); in parseGenericRegister() 100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister() 111 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local 114 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
D | AArch64BaseInfo.cpp | 122 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local 128 Ops[5].getAsInteger(10, Op2); in parseGenericRegister() 129 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister() 140 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local 143 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | DFAPacketizer.cpp | 342 const MachineMemOperand &Op2, in alias() argument 344 if (!Op1.getValue() || !Op2.getValue()) in alias() 347 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias() 349 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; in alias() 354 MemoryLocation(Op2.getValue(), Overlapb, in alias() 355 UseTBAA ? Op2.getAAInfo() : AAMDNodes())); in alias() 367 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local 368 if (alias(*Op1, *Op2, UseTBAA)) in alias()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | SelectionDAGTargetInfo.h | 54 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument 70 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument 83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument 95 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument 132 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
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/external/llvm/include/llvm/CodeGen/ |
D | SelectionDAGTargetInfo.h | 51 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument 67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument 80 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument 92 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument 129 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
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/external/tensorflow/tensorflow/core/api_def/ |
D | update_api_def_test.cc | 83 REGISTER_OP("Op2") in TEST() 100 REGISTER_OP("Op2") in TEST() 104 Summary for Op2. in TEST() 123 name: "Op2" in TEST() 127 summary: "Summary for Op2." in TEST()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/AsmParser/ |
D | BPFAsmParser.cpp | 268 BPFOperand &Op2 = (BPFOperand &)*Operands[2]; in PreMatchCheck() local 270 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck() 272 && (Op2.getToken() == "-" || Op2.getToken() == "be16" in PreMatchCheck() 273 || Op2.getToken() == "be32" || Op2.getToken() == "be64" in PreMatchCheck() 274 || Op2.getToken() == "le16" || Op2.getToken() == "le32" in PreMatchCheck() 275 || Op2.getToken() == "le64") in PreMatchCheck()
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/external/swiftshader/third_party/LLVM/include/llvm/Target/ |
D | TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy() argument 76 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument 92 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemset() argument
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonSplitDouble.cpp | 347 const MachineOperand &Op2 = MI->getOperand(2); in profit() local 349 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0; in profit() 732 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local 749 if (!Op2.isReg()) { in splitCombine() 751 .add(Op2); in splitCombine() 754 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine() 784 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local 785 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift() 786 int64_t Sh64 = Op2.getImm(); in splitShift() 908 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
D | X86AsmParser.cpp | 816 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local 817 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) { in ParseInstruction() 821 delete &Op2; in ParseInstruction() 829 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local 830 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) { in ParseInstruction() 834 delete &Op2; in ParseInstruction() 843 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local 844 if (isSrcOp(Op) && isDstOp(Op2)) { in ParseInstruction() 848 delete &Op2; in ParseInstruction() 856 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); in ParseInstruction() local [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/unittests/ADT/ |
D | APFloatTest.cpp | 3360 uint64_t Op1[2], Op2[2]; in TEST() local 3363 std::tie(Op1[0], Op1[1], Op2[0], Op2[1], Expected, RM) = Tp; in TEST() 3367 APFloat A2(APFloat::PPCDoubleDouble(), APInt(128, 2, Op2)); in TEST() 3372 Op2[0], Op2[1]) in TEST() 3377 APFloat A2(APFloat::PPCDoubleDouble(), APInt(128, 2, Op2)); in TEST() 3381 << formatv("({0:x} + {1:x}) + ({2:x} + {3:x})", Op2[0], Op2[1], in TEST() 3425 uint64_t Op1[2], Op2[2], Expected[2]; in TEST() local 3427 std::tie(Op1[0], Op1[1], Op2[0], Op2[1], Expected[0], Expected[1], RM) = Tp; in TEST() 3431 APFloat A2(APFloat::PPCDoubleDouble(), APInt(128, 2, Op2)); in TEST() 3436 Op2[0], Op2[1]) in TEST() [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonSplitDouble.cpp | 688 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local 706 if (Op2.isImm()) { in splitCombine() 708 .addImm(Op2.getImm()); in splitCombine() 709 } else if (Op2.isReg()) { in splitCombine() 711 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine() 742 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local 743 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift() 744 int64_t Sh64 = Op2.getImm(); in splitShift() 866 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local 868 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr() [all …]
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | SelectionDAG.h | 484 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, 490 Ops.push_back(Op2); 708 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); 709 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 711 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 713 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 725 SDValue Op1, SDValue Op2); 727 SDValue Op1, SDValue Op2, SDValue Op3); 741 EVT VT2, SDValue Op1, SDValue Op2); 743 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); [all …]
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
D | AArch64InstPrinter.cpp | 69 const MCOperand &Op2 = MI->getOperand(2); in printInst() local 74 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst() 110 if (Op2.isImm() && Op3.isImm()) { in printInst() 113 int64_t immr = Op2.getImm(); in printInst() 144 if (Op2.getImm() > Op3.getImm()) { in printInst() 147 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst() 155 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst() 162 const MCOperand &Op2 = MI->getOperand(2); in printInst() local 166 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && in printInst() 184 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width; in printInst() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Utils/ |
D | BypassSlowDivision.cpp | 90 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2); 329 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument 330 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck() 334 if (Op1 && Op2) in insertOperandRuntimeCheck() 335 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck() 337 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
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