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Searched refs:Pat (Results 1 – 25 of 231) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrMemory.td77 def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr, 0)>;
78 def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr, 0)>;
79 def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr, 0)>;
80 def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr, 0)>;
83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
87 def : Pat<(f32 (load (regPlusImm I32:$addr, imm:$off))),
89 def : Pat<(f64 (load (regPlusImm I32:$addr, imm:$off))),
91 def : Pat<(i32 (load (or_is_add I32:$addr, imm:$off))),
93 def : Pat<(i64 (load (or_is_add I32:$addr, imm:$off))),
[all …]
DWebAssemblyInstrFloat.td42 def : Pat<(fcopysign F64:$lhs, F32:$rhs),
44 def : Pat<(fcopysign F32:$lhs, F64:$rhs),
48 def : Pat<(frint f32:$src), (NEAREST_F32 f32:$src)>;
49 def : Pat<(frint f64:$src), (NEAREST_F64 f64:$src)>;
65 def : Pat<(seteq f32:$lhs, f32:$rhs), (EQ_F32 f32:$lhs, f32:$rhs)>;
66 def : Pat<(setne f32:$lhs, f32:$rhs), (NE_F32 f32:$lhs, f32:$rhs)>;
67 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>;
68 def : Pat<(setle f32:$lhs, f32:$rhs), (LE_F32 f32:$lhs, f32:$rhs)>;
69 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>;
70 def : Pat<(setge f32:$lhs, f32:$rhs), (GE_F32 f32:$lhs, f32:$rhs)>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonMapAsm2IntrinV65.gen.td10 def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany Dou…
11 def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat …
12 def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwu…
13 def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat …
14 def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhu…
15 def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubr…
16 def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasr…
17 def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>;
18 def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX…
19 def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, Use…
[all …]
DHexagonPatternsHVX.td101 def: Pat<(ResType (Load I32:$Rt)),
103 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
108 def: Pat<(ResType (Load (HexagonCP tconstpool:$A))),
110 def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))),
117 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
119 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
143 def: Pat<(Store Value:$Vs, I32:$Rt),
145 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
166 : Pat<(ResTy (bitconvert (InpTy RC:$Val))), (ResTy RC:$Val)>;
185 def: Pat<(VecI8 vzero), (V6_vd0)>;
[all …]
DHexagonMapAsm2IntrinV62.gen.td11 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
13 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
18 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
20 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
26 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
28 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
33 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
35 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
40 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
42 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
[all …]
DHexagonIntrinsicsV60.td16 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
19 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
22 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
25 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
29 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
32 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
35 def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))),
38 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
41 def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
44 def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))),
[all …]
DHexagonPatterns.td249 def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off),
267 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;
271 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)),
276 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
281 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)),
286 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
291 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B),
293 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A),
320 def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>;
321 def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td11 // compiler, as well as Pat patterns used during instruction selection.
21 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
22 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
23 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
24 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
25 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
27 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
28 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
29 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
[all …]
DX86InstrCompiler.td11 // as well as Pat patterns used during instruction selection.
59 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
77 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
283 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
284 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
285 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;
302 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
303 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
330 def : Pat<(i64 mov64imm32:$src),
335 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td17 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
18 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
44 def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
45 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
48 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
51 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
54 def : Pat<(relaxed_load<atomic_load_8>
59 def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
60 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
63 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
[all …]
DAArch64InstrInfo.td372 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
375 def : Pat<(AArch64LOADgot texternalsym:$addr),
378 def : Pat<(AArch64LOADgot tconstpool:$addr),
424 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
428 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
548 def : Pat<(i64 i64imm_32bit:$src),
563 def : Pat<(f32 fpimm:$in),
565 def : Pat<(f64 fpimm:$in),
571 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
578 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td20 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
21 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
47 def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
48 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
51 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
54 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
57 def : Pat<(relaxed_load<atomic_load_8>
62 def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
63 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
66 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
[all …]
DAArch64InstrInfo.td421 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
424 def : Pat<(AArch64LOADgot texternalsym:$addr),
427 def : Pat<(AArch64LOADgot tconstpool:$addr),
621 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
624 def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>;
747 def : Pat<(i64 i64imm_32bit:$src),
762 def : Pat<(f32 fpimm:$in),
764 def : Pat<(f64 fpimm:$in),
770 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
777 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrCompiler.td11 // as well as Pat patterns used during instruction selection.
199 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
200 // However, Pat<> can't replicate the destination reg into the inputs of the
216 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
218 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
220 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
223 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
225 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
227 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
234 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td958 def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
961 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
964 def : Pat<(f64 (extractelt v2f64:$S, 0)),
966 def : Pat<(f64 (extractelt v2f64:$S, 1)),
971 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
975 def : Pat<(f64 (extractelt v2f64:$S, 0)),
977 def : Pat<(f64 (extractelt v2f64:$S, 1)),
982 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
984 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
987 def : Pat<(fma (fneg v2f64:$A), v2f64:$C, v2f64:$B),
[all …]
DPPCInstrHTM.td96 def : Pat<(int_ppc_tbegin i32:$R),
102 def : Pat<(int_ppc_tend i32:$R),
106 def : Pat<(int_ppc_tabort i32:$R),
109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
121 def : Pat<(int_ppc_tcheck),
124 def : Pat<(int_ppc_treclaim i32:$RA),
127 def : Pat<(int_ppc_trechkpt),
[all …]
DPPCInstrQPX.td837 def : Pat<(v4f64 (scalar_to_vector f64:$A)),
839 def : Pat<(v4f32 (scalar_to_vector f32:$A)),
842 def : Pat<(f64 (extractelt v4f64:$S, 0)),
844 def : Pat<(f32 (extractelt v4f32:$S, 0)),
847 def : Pat<(f64 (extractelt v4f64:$S, 1)),
849 def : Pat<(f64 (extractelt v4f64:$S, 2)),
851 def : Pat<(f64 (extractelt v4f64:$S, 3)),
854 def : Pat<(f32 (extractelt v4f32:$S, 1)),
856 def : Pat<(f32 (extractelt v4f32:$S, 2)),
858 def : Pat<(f32 (extractelt v4f32:$S, 3)),
[all …]
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td11 // as well as Pat patterns used during instruction selection.
55 def : Pat<(X86callseq_start timm:$amt1),
74 def : Pat<(X86callseq_start timm:$amt1),
268 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
269 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
270 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
286 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
287 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
314 def : Pat<(i64 mov64imm32:$src),
319 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrHTM.td96 def : Pat<(int_ppc_tbegin i32:$R),
102 def : Pat<(int_ppc_tend i32:$R),
106 def : Pat<(int_ppc_tabort i32:$R),
109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
121 def : Pat<(int_ppc_tcheck),
124 def : Pat<(int_ppc_treclaim i32:$RA),
127 def : Pat<(int_ppc_trechkpt),
[all …]
DPPCInstrQPX.td837 def : Pat<(v4f64 (scalar_to_vector f64:$A)),
839 def : Pat<(v4f32 (scalar_to_vector f32:$A)),
842 def : Pat<(f64 (extractelt v4f64:$S, 0)),
844 def : Pat<(f32 (extractelt v4f32:$S, 0)),
847 def : Pat<(f64 (extractelt v4f64:$S, 1)),
849 def : Pat<(f64 (extractelt v4f64:$S, 2)),
851 def : Pat<(f64 (extractelt v4f64:$S, 3)),
854 def : Pat<(f32 (extractelt v4f32:$S, 1)),
856 def : Pat<(f32 (extractelt v4f32:$S, 2)),
858 def : Pat<(f32 (extractelt v4f32:$S, 3)),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td22 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
40 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
43 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
44 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
69 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
75 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
93 def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td22 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
40 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
43 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
44 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
69 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
75 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
93 def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td25 def : Pat <(b (bitconvert (a IntRegs:$src))),
27 def : Pat <(a (bitconvert (b IntRegs:$src))),
32 def : Pat <(b (bitconvert (a DoubleRegs:$src))),
34 def : Pat <(a (bitconvert (b DoubleRegs:$src))),
69 def : Pat<(v2i16 (add (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
72 def : Pat<(v2i16 (sub (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
89 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
93 def: Pat<(v4i16 (HexagonVSPLATH I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
97 : Pat <(Op Type:$Rss, Type:$Rtt),
121 def: Pat<(v2i32 (sra V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
[all …]
DHexagonIntrinsicsV60.td65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
84 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
89 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
94 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
99 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
104 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
109 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFloat.td42 def : Pat<(fcopysign F64:$lhs, F32:$rhs),
44 def : Pat<(fcopysign F32:$lhs, F64:$rhs),
48 def : Pat<(frint f32:$src), (NEAREST_F32 f32:$src)>;
49 def : Pat<(frint f64:$src), (NEAREST_F64 f64:$src)>;
65 def : Pat<(seteq f32:$lhs, f32:$rhs), (EQ_F32 f32:$lhs, f32:$rhs)>;
66 def : Pat<(setne f32:$lhs, f32:$rhs), (NE_F32 f32:$lhs, f32:$rhs)>;
67 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>;
68 def : Pat<(setle f32:$lhs, f32:$rhs), (LE_F32 f32:$lhs, f32:$rhs)>;
69 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>;
70 def : Pat<(setge f32:$lhs, f32:$rhs), (GE_F32 f32:$lhs, f32:$rhs)>;
[all …]

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