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Searched refs:SLOT1 (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepIICScalar.td179 InstrItinData <tc_03220ffa, [InstrStage<1, [SLOT0, SLOT1]>]>,
182 InstrItinData <tc_05b6c987, [InstrStage<1, [SLOT0, SLOT1]>]>,
183 InstrItinData <tc_0cd51c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
184 InstrItinData <tc_0dc560de, [InstrStage<1, [SLOT0, SLOT1]>]>,
193 InstrItinData <tc_1b82a277, [InstrStage<1, [SLOT0, SLOT1]>]>,
195 InstrItinData <tc_1d5a38a8, [InstrStage<1, [SLOT0, SLOT1]>]>,
198 InstrItinData <tc_238d91d2, [InstrStage<1, [SLOT0, SLOT1]>]>,
201 InstrItinData <tc_2b2f4060, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
204 InstrItinData <tc_2fc0c436, [InstrStage<1, [SLOT0, SLOT1]>]>,
208 InstrItinData <tc_36c68ad1, [InstrStage<1, [SLOT0, SLOT1]>]>,
[all …]
DHexagonDepIICHVX.td109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
114 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
124 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
130 InstrStage<1, [SLOT1], 0>,
137 InstrStage<1, [SLOT1], 0>,
143 [InstrStage<1, [SLOT0, SLOT1], 0>,
148 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
153 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
163 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
168 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
[all …]
DHexagonScheduleV55.td13 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
25 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>,
26 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
35 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonScheduleV4.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
25 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
26 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>
33 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonIICScalar.td16 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
27 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
29 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
DHexagonScheduleV60.td19 // | SLOT1 | LD ST ALU32 |
65 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonIICHVX.td16 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
DHexagonScheduleV62.td21 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV65.td23 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonSchedule.td15 def SLOT1 : FuncUnit;
DHexagonInstrFormats.td209 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV60.td69 // | SLOT1 | LD ST ALU32 |
107 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
112 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
114 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
116 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
118 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
120 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
122 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
149 [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
152 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
[all …]
DHexagonScheduleV55.td19 // | SLOT1 | LD ST ALU32 |
43 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
46 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
48 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
50 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
52 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
54 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
56 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
83 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
86 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
[all …]
DHexagonScheduleV4.td19 // | SLOT1 | LD ST ALU32 |
28 def SLOT1 : FuncUnit;
100 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
103 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
105 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
107 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
111 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
113 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
137 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
[all …]
DHexagonInstrFormats.td240 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
263 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
270 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dbr-cond-not-merge.ll70 ; NOOPT: str [[R1]], [sp, #[[SLOT1:[0-9]+]]]
72 ; NOOPT: ldr [[R2:w[0-9]+]], [sp, #[[SLOT1]]]
/external/python/cpython3/Objects/
Dtypeobject.c5958 #define SLOT1(FUNCNAME, OPSTR, ARG1TYPE) \ macro
6147 SLOT1(slot_mp_subscript, "__getitem__", PyObject *)
6275 SLOT1(slot_nb_inplace_add, "__iadd__", PyObject *)
6276 SLOT1(slot_nb_inplace_subtract, "__isub__", PyObject *)
6277 SLOT1(slot_nb_inplace_multiply, "__imul__", PyObject *)
6278 SLOT1(slot_nb_inplace_matrix_multiply, "__imatmul__", PyObject *)
6279 SLOT1(slot_nb_inplace_remainder, "__imod__", PyObject *)
6288 SLOT1(slot_nb_inplace_lshift, "__ilshift__", PyObject *)
6289 SLOT1(slot_nb_inplace_rshift, "__irshift__", PyObject *)
6290 SLOT1(slot_nb_inplace_and, "__iand__", PyObject *)
[all …]
/external/python/cpython2/Objects/
Dtypeobject.c5026 #define SLOT1(FUNCNAME, OPSTR, ARG1TYPE, ARGCODES) \ macro
5271 SLOT1(slot_mp_subscript, "__getitem__", PyObject *, "O")
5445 SLOT1(slot_nb_inplace_add, "__iadd__", PyObject *, "O")
5446 SLOT1(slot_nb_inplace_subtract, "__isub__", PyObject *, "O")
5447 SLOT1(slot_nb_inplace_multiply, "__imul__", PyObject *, "O")
5448 SLOT1(slot_nb_inplace_divide, "__idiv__", PyObject *, "O")
5449 SLOT1(slot_nb_inplace_remainder, "__imod__", PyObject *, "O")
5457 SLOT1(slot_nb_inplace_lshift, "__ilshift__", PyObject *, "O")
5458 SLOT1(slot_nb_inplace_rshift, "__irshift__", PyObject *, "O")
5459 SLOT1(slot_nb_inplace_and, "__iand__", PyObject *, "O")
[all …]