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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td30 def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
68 defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">;
73 defm UMAX_ZI : sve_int_arith_imm1<0b01, "umax", imm0_255>;
155 defm FMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b01, "fmls">;
160 defm FMSB_ZPmZZ : sve_fp_3op_p_zds_b<0b01, "fmsb">;
216 defm SUNPKHI_ZZ : sve_int_perm_unpk<0b01, "sunpkhi">;
232 def BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb">;
298 defm LD1RB_H_IMM : sve_mem_ld_dup<0b00, 0b01, "ld1rb", Z_h, ZPR16, uimm6s1>;
301 defm LD1RSW_IMM : sve_mem_ld_dup<0b01, 0b00, "ld1rsw", Z_d, ZPR64, uimm6s4>;
302 defm LD1RH_IMM : sve_mem_ld_dup<0b01, 0b01, "ld1rh", Z_h, ZPR16, uimm6s2>;
[all …]
DSVEInstrFormats.td264 def _H : sve_int_ptrue<0b01, opc, asm, PPR16>;
347 def : sve_int_pfirst_next<0b01, opc, asm, PPR8>;
352 def _H : sve_int_pfirst_next<0b01, opc, asm, PPR16>;
387 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64as32>;
394 def _H : sve_int_count_r<0b01, opc, asm, GPR32z, PPR16, GPR32z>;
401 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>;
429 def _H : sve_int_count_v<0b01, opc, asm, ZPR16>;
456 def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>;
629 def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, GPR32sp>;
724 def _H : sve_int_perm_tbl<0b01, asm, ZPR16, Z_h>;
[all …]
DAArch64InstrInfo.td481 def SHA512H2 : CryptoRRRTied<0b0, 0b01, "sha512h2">;
486 def BCAX : CryptoRRRR_16B<0b01, "bcax">;
492 def SM3TT1B : CryptoRRRi2Tied<0b0, 0b01, "sm3tt1b">;
497 def SM3PARTW2 : CryptoRRRTied_4S<0b1, 0b01, "sm3partw2">;
499 def SM4E : CryptoRRTied_4S<0b0, 0b01, "sm4e">;
505 def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>;
549 def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>;
554 def IZB : SignAuthZero<prefix_z, 0b01, !strconcat(asm, "izb")>;
562 def XPACD : SignAuthZero<0b100, 0b01, "xpacd">;
588 def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
[all …]
DAArch64InstrFormats.td1242 let Inst{20-19} = 0b01;
1257 let Inst{20-19} = 0b01;
2776 let Inst{25-24} = 0b01;
3594 let Inst{11-10} = 0b01;
4026 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
4032 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
4077 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
4086 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
4148 let Inst{23-22} = 0b01; // 64-bit FPR flag
4164 let Inst{23-22} = 0b01; // 64-bit FPR flag
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
39 def : AT<"S1E2W", 0b01, 0b100, 0b0111, 0b1000, 0b001>;
40 def : AT<"S1E3W", 0b01, 0b110, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
43 def : AT<"S12E1R", 0b01, 0b100, 0b0111, 0b1000, 0b100>;
44 def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>;
[all …]
DAArch64InstrInfo.td704 defm LSRV : Shift<0b01, "lsr", srl>;
802 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
807 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
888 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
909 defm ORN : LogicalReg<0b01, 1, "orn",
911 defm ORR : LogicalReg<0b01, 0, "orr", or>;
1004 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
1115 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1117 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1276 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
[all …]
DAArch64InstrFormats.td1020 let Inst{20-19} = 0b01;
1035 let Inst{20-19} = 0b01;
2402 let Inst{25-24} = 0b01;
3163 let Inst{11-10} = 0b01;
3595 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3601 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3646 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3655 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3717 let Inst{23-22} = 0b01; // 64-bit FPR flag
3733 let Inst{23-22} = 0b01; // 64-bit FPR flag
[all …]
/external/tcpdump/tests/
Disis_sysid_asan.out6 0x0000: ff10 8e12 0001 1b01 0000 6b00 fbcf f90f
8 0x0020: 0281 0083 1b01 0010 019d e000 fed0 f90f
10 0x0040: 0c2a 2205 831b 011c 0010 0000 0583 1b01
/external/skia/src/core/
DSkMatrix44.cpp456 double b01 = a00 * a12 - a02 * a10; in determinant() local
469 return b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in determinant()
571 double b01 = a00 * a12 - a02 * a10; in invert() local
581 double det = b00 * b11 - b01 * b10 + b03 * b08; in invert()
592 b01 *= invdet; in invert()
607 inverse->fMat[1][2] = SkDoubleToMScalar(-b01); in invert()
615 inverse->fMat[3][2] = SkDoubleToMScalar(a31 * b01 - a30 * b03 - a32 * b00); in invert()
629 double b01 = a00 * a12 - a02 * a10; in invert() local
642 double det = b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in invert()
653 b01 *= invdet; in invert()
[all …]
/external/skqp/src/core/
DSkMatrix44.cpp456 double b01 = a00 * a12 - a02 * a10; in determinant() local
469 return b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in determinant()
571 double b01 = a00 * a12 - a02 * a10; in invert() local
581 double det = b00 * b11 - b01 * b10 + b03 * b08; in invert()
592 b01 *= invdet; in invert()
607 inverse->fMat[1][2] = SkDoubleToMScalar(-b01); in invert()
615 inverse->fMat[3][2] = SkDoubleToMScalar(a31 * b01 - a30 * b03 - a32 * b00); in invert()
629 double b01 = a00 * a12 - a02 * a10; in invert() local
642 double det = b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in invert()
653 b01 *= invdet; in invert()
[all …]
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td398 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
403 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
408 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
413 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
418 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
423 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
432 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
437 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
442 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
447 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td396 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
401 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
406 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
411 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
416 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
421 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
430 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
435 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
440 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
445 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td238 : RVInst16CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm),
252 : RVInst16CB<0b100, 0b01, (outs cls:$rs1_wb), (ins cls:$rs1, ImmOpnd:$imm),
263 : RVInst16CS<0b100, 0b01, (outs cls:$rd_wb), (ins cls:$rd, cls:$rs2),
351 def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">;
354 def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
364 def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
369 def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
377 def C_LI : RVInst16CI<0b010, 0b01, (outs GPRNoX0:$rd), (ins simm6:$imm),
383 def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),
396 def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX0X2:$rd),
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td101 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),
148 let Inst{24-23} = 0b01; // Increment After
157 let Inst{24-23} = 0b01; // Increment After
176 let Inst{24-23} = 0b01; // Increment After
189 let Inst{24-23} = 0b01; // Increment After
302 let Inst{24-23} = 0b01; // Increment After
309 let Inst{24-23} = 0b01; // Increment After
465 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
[all …]
DARMInstrNEON.td3239 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3253 def v4f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3266 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3280 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3299 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3307 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3323 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3340 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3355 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3374 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrVFP.td121 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
125 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
133 def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),
168 let Inst{24-23} = 0b01; // Increment After
177 let Inst{24-23} = 0b01; // Increment After
196 let Inst{24-23} = 0b01; // Increment After
209 let Inst{24-23} = 0b01; // Increment After
302 let Inst{24-23} = 0b01; // Increment After
309 let Inst{24-23} = 0b01; // Increment After
480 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
[all …]
DARMInstrNEON.td3330 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3344 def v4f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3357 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3371 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3390 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3398 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3414 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3431 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3446 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3465 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
[all …]
DARMInstrThumb2.td605 let Inst{26-25} = 0b01;
618 let Inst{26-25} = 0b01;
689 let Inst{26-25} = 0b01;
702 let Inst{26-25} = 0b01;
809 let Inst{26-25} = 0b01;
823 let Inst{26-25} = 0b01;
852 let Inst{26-25} = 0b01;
865 let Inst{26-25} = 0b01;
948 let Inst{26-25} = 0b01;
963 let Inst{26-25} = 0b01;
[all …]
/external/clang/test/CodeGenCXX/
Dbitfield.cpp14 unsigned b01 : 2; member
52 return s->b01; in read01()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td71 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
75 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
108 let Inst{24-23} = 0b01; // Increment After
117 let Inst{24-23} = 0b01; // Increment After
136 let Inst{24-23} = 0b01; // Increment After
149 let Inst{24-23} = 0b01; // Increment After
289 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
294 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
344 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
352 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
[all …]
DARMInstrNEON.td2512 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2532 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2558 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2566 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2582 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2599 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2614 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2633 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2644 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2653 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
[all …]
DARMInstrThumb2.td511 let Inst{26-25} = 0b01;
523 let Inst{26-25} = 0b01;
589 let Inst{26-25} = 0b01;
601 let Inst{26-25} = 0b01;
677 let Inst{26-25} = 0b01;
690 let Inst{26-25} = 0b01;
719 let Inst{26-25} = 0b01;
732 let Inst{26-25} = 0b01;
840 let Inst{26-25} = 0b01;
854 let Inst{26-25} = 0b01;
[all …]
/external/perfetto/src/traced/probes/ftrace/
Dcpu_reader_unittest.cc1647 00000760: 1b01 0001 8406 0000 2000 3010 0400 0000 ........ .0..... in TEST()
1656 000007f0: 28b2 1e00 1b01 0001 8406 0000 2000 3010 (........... .0. in TEST()
1674 00000910: 0000 0000 a85a 1600 1b01 0001 8015 0000 .....Z.......... in TEST()
1693 00000a40: 1b01 0001 8015 0000 2000 3010 6606 3200 ........ .0.f.2.
1734 00000cd0: a847 0000 1b01 0001 8015 0000 2000 3010 .G.......... .0.
1736 00000cf0: 91ff ffff e83a 0300 1b01 0001 8015 0000 .....:..........
1742 00000d50: 0000 0000 48b6 0000 1b01 0001 8015 0000 ....H...........
1744 00000d70: 9c99 ea6a 91ff ffff a8ea 0300 1b01 0001 ...j............
1751 00000de0: 0000 0000 c895 0000 1b01 0001 8015 0000 ................
1769 00000f00: 8c11 0100 6b01 0001 8015 0000 2000 3010 ....k....... .0.
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td93 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
500 let Inst{25-24} = !if(isHi, 0b10, 0b01);
1088 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1094 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1101 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1107 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1156 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1358 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1569 let Inst{24-23} = !if (isPred, 0b10, 0b01);
2202 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
[all …]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-CPS2p-arm.txt3 # invalid imod value (0b01)

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