/external/elfutils/tests/ |
D | run-allregs.sh | 32 0: %eax (eax), signed 32 bits 33 1: %ecx (ecx), signed 32 bits 34 2: %edx (edx), signed 32 bits 35 3: %ebx (ebx), signed 32 bits 36 4: %esp (esp), address 32 bits 37 5: %ebp (ebp), address 32 bits 38 6: %esi (esi), signed 32 bits 39 7: %edi (edi), signed 32 bits 40 8: %eip (eip), address 32 bits 41 9: %eflags (eflags), unsigned 32 bits [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonDepInstrFormats.td | 14 bits <5> Rs32; 16 bits <5> Rd32; 18 bits <2> Pe4; 22 bits <2> Qs4; 24 bits <5> Rt32; 26 bits <1> Mu2; 28 bits <5> Vv32; 30 bits <5> Vw32; 34 bits <2> Ps4; 36 bits <2> Pt4; [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MicroMipsInstrFormats.td | 48 field bits<16> Inst; 49 field bits<16> SoftFail = 0; 50 bits<6> Opcode = 0x0; 58 bits<3> rd; 59 bits<3> rt; 60 bits<3> rs; 62 bits<16> Inst; 71 class ANDI_FM_MM16<bits<6> funct> { 72 bits<3> rd; 73 bits<3> rs; [all …]
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D | MicroMips32r6InstrFormats.td | 39 bits<10> offset; 41 bits<16> Inst; 47 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> { 48 bits<3> rs; 49 bits<7> offset; 51 bits<16> Inst; 58 class POOL16C_JALRC_FM_MM16R6<bits<5> op> { 59 bits<5> rs; 61 bits<16> Inst; 69 bits<5> rt; [all …]
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D | MipsMSAInstrFormats.td | 31 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst { 32 bits<5> ws; 33 bits<5> wd; 34 bits<3> m; 44 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst { 45 bits<5> ws; 46 bits<5> wd; 47 bits<4> m; 57 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst { 58 bits<5> ws; [all …]
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D | MipsInstrFormats.td | 27 class Format<bits<4> val> { 28 bits<4> Value = val; 75 field bits<32> Inst; 82 bits<6> Opcode = 0; 84 // Top 6 bits are the 'opcode' field 97 bits<4> FormBits = Form.Value; 116 field bits<32> SoftFail = 0; 155 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 159 bits<5> rd; 160 bits<5> rs; [all …]
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D | MicroMipsDSPInstrFormats.td | 25 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> { 26 bits<5> rd; 27 bits<5> rs; 28 bits<5> rt; 37 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> { 38 bits<5> rt; 39 bits<5> rs; 48 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> { 49 bits<5> rt; 50 bits<5> rs; [all …]
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D | Mips32r6InstrFormats.td | 44 class OPGROUP<bits<6> Val> { 45 bits<6> Value = Val; 66 class OPCODE2<bits<2> Val> { 67 bits<2> Value = Val; 73 class OPCODE3<bits<3> Val> { 74 bits<3> Value = Val; 78 class OPCODE5<bits<5> Val> { 79 bits<5> Value = Val; 97 class OPCODE6<bits<6> Val> { 98 bits<6> Value = Val; [all …]
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/external/llvm/lib/Target/Mips/ |
D | MicroMipsInstrFormats.td | 35 field bits<16> Inst; 36 field bits<16> SoftFail = 0; 37 bits<6> Opcode = 0x0; 45 bits<3> rd; 46 bits<3> rt; 47 bits<3> rs; 49 bits<16> Inst; 58 class ANDI_FM_MM16<bits<6> funct> { 59 bits<3> rd; 60 bits<3> rs; [all …]
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D | MicroMips32r6InstrFormats.td | 45 bits<10> offset; 47 bits<16> Inst; 53 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 { 54 bits<3> rs; 55 bits<7> offset; 57 bits<16> Inst; 64 class POOL16C_JALRC_FM_MM16R6<bits<5> op> { 65 bits<5> rs; 67 bits<16> Inst; 75 bits<5> rt; [all …]
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D | MipsMSAInstrFormats.td | 30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst { 31 bits<5> ws; 32 bits<5> wd; 33 bits<3> m; 43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst { 44 bits<5> ws; 45 bits<5> wd; 46 bits<4> m; 56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst { 57 bits<5> ws; [all …]
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D | MipsInstrFormats.td | 27 class Format<bits<4> val> { 28 bits<4> Value = val; 75 field bits<32> Inst; 82 bits<6> Opcode = 0; 84 // Top 6 bits are the 'opcode' field 97 bits<4> FormBits = Form.Value; 109 field bits<32> SoftFail = 0; 148 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 152 bits<5> rd; 153 bits<5> rs; [all …]
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D | MicroMips64r6InstrFormats.td | 15 bits<5> rt; 16 bits<5> rs; 17 bits<16> imm; 19 bits<32> Inst; 27 class POOL32I_ADD_IMM_FM_MMR6<bits<5> funct> { 28 bits<5> rs; 29 bits<16> imm; 31 bits<32> Inst; 39 class POOL32S_EXTBITS_FM_MMR6<bits<6> funct> { 40 bits<5> rt; [all …]
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D | MicroMipsDSPInstrFormats.td | 25 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> { 26 bits<5> rd; 27 bits<5> rs; 28 bits<5> rt; 37 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> { 38 bits<5> rt; 39 bits<5> rs; 48 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> { 49 bits<5> rt; 50 bits<5> rs; [all …]
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D | Mips32r6InstrFormats.td | 45 class OPGROUP<bits<6> Val> { 46 bits<6> Value = Val; 66 class OPCODE2<bits<2> Val> { 67 bits<2> Value = Val; 73 class OPCODE3<bits<3> Val> { 74 bits<3> Value = Val; 78 class OPCODE5<bits<5> Val> { 79 bits<5> Value = Val; 97 class OPCODE6<bits<6> Val> { 98 bits<6> Value = Val; [all …]
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/external/llvm/lib/Target/AMDGPU/ |
D | R600InstrFormats.td | 18 field bits<64> Inst; 22 bits<2> FlagOperandIdx = 0; 68 field bits<32> Word0; 70 bits<11> src0; 71 bits<1> src0_rel; 72 bits<11> src1; 73 bits<1> src1_rel; 74 bits<3> index_mode = 0; 75 bits<2> pred_sel; 76 bits<1> last; [all …]
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D | VIInstrFormats.td | 14 class DSe_vi <bits<8> op> : Enc64 { 15 bits<8> vdst; 16 bits<1> gds; 17 bits<8> addr; 18 bits<8> data0; 19 bits<8> data1; 20 bits<8> offset0; 21 bits<8> offset1; 34 class MUBUFe_vi <bits<7> op> : Enc64 { 35 bits<12> offset; [all …]
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D | SIInstrFormats.td | 18 field bits<1> VM_CNT = 0; 19 field bits<1> EXP_CNT = 0; 20 field bits<1> LGKM_CNT = 0; 22 field bits<1> SALU = 0; 23 field bits<1> VALU = 0; 25 field bits<1> SOP1 = 0; 26 field bits<1> SOP2 = 0; 27 field bits<1> SOPC = 0; 28 field bits<1> SOPK = 0; 29 field bits<1> SOPP = 0; [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | R600InstrFormats.td | 27 field bits<64> Inst; 31 bits<2> FlagOperandIdx = 0; 78 field bits<32> Word0; 80 bits<11> src0; 81 bits<1> src0_rel; 82 bits<11> src1; 83 bits<1> src1_rel; 84 bits<3> index_mode = 0; 85 bits<2> pred_sel; 86 bits<1> last; [all …]
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/external/llvm/test/TableGen/ |
D | BitsInit.td | 6 bits<2> opc = { 0, 1 }; 7 bits<2> opc2 = { 1, 0 }; 8 bits<1> opc3 = { 1 }; 9 bits<2> a = { opc, opc2 }; // error! 10 bits<2> b = { opc{0}, opc2{0} }; 11 bits<2> c = { opc{1}, opc2{1} }; 12 bits<2> c = { opc3{0}, opc3 }; 16 // CHECK: bits<2> opc = { 0, 1 }; 17 // CHECK: bits<2> opc2 = { 1, 0 }; 18 // CHECK: bits<1> opc3 = { 1 }; [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
D | BitsInit.td | 6 bits<2> opc = { 0, 1 }; 7 bits<2> opc2 = { 1, 0 }; 8 bits<1> opc3 = { 1 }; 9 bits<2> a = { opc, opc2 }; // error! 10 bits<2> b = { opc{0}, opc2{0} }; 11 bits<2> c = { opc{1}, opc2{1} }; 12 bits<2> c = { opc3{0}, opc3 }; 16 // CHECK: bits<2> opc = { 0, 1 }; 17 // CHECK: bits<2> opc2 = { 1, 0 }; 18 // CHECK: bits<1> opc3 = { 1 }; [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCInstrFormats.td | 14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 46 bits<1> UseVSXReg = 0; 50 bits<1> XFormMemOp = 0; 63 class PPC970_DGroup_First { bits<1> PPC970_First = 1; } [all …]
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/external/u-boot/board/micronas/vct/ |
D | dcgu.c | 40 en1.bits.en_clkmsmc = enable; in dcgu_set_clk_switch() 43 en1.bits.en_clkssi_s = enable; in dcgu_set_clk_switch() 46 en1.bits.en_clkssi_m = enable; in dcgu_set_clk_switch() 49 en1.bits.en_clksmc = enable; in dcgu_set_clk_switch() 52 en1.bits.en_clkebi = enable; in dcgu_set_clk_switch() 55 en1.bits.en_usbpll = enable; in dcgu_set_clk_switch() 58 en1.bits.en_clkusb60 = enable; in dcgu_set_clk_switch() 61 en1.bits.en_clkusb24 = enable; in dcgu_set_clk_switch() 64 en1.bits.en_clkuart2 = enable; in dcgu_set_clk_switch() 67 en1.bits.en_clkuart1 = enable; in dcgu_set_clk_switch() [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrFormats.td | 14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCInstrFormats.td | 14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 16 field bits<32> Inst; 27 bits<1> PPC970_First = 0; 28 bits<1> PPC970_Single = 0; 29 bits<1> PPC970_Cracked = 0; 30 bits<3> PPC970_Unit = 0; 40 class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 41 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 42 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 45 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } [all …]
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