| /external/mesa3d/src/gallium/state_trackers/omx_bellagio/ |
| D | vid_dec_mpeg12.c | 62 static void vid_dec_mpeg12_Decode(vid_dec_PrivateType *priv, struct vl_vlc *vlc, unsigned min_bits_…
63 static void vid_dec_mpeg12_EndFrame(vid_dec_PrivateType *priv);
64 static struct pipe_video_buffer *vid_dec_mpeg12_Flush(vid_dec_PrivateType *priv, OMX_TICKS *timesta…
66 void vid_dec_mpeg12_Init(vid_dec_PrivateType *priv) in vid_dec_mpeg12_Init() argument
71 port = (omx_base_video_PortType *)priv->ports[OMX_BASE_FILTER_INPUTPORT_INDEX]; in vid_dec_mpeg12_Init()
72 templat.profile = priv->profile; in vid_dec_mpeg12_Init()
80 priv->codec = priv->pipe->create_video_codec(priv->pipe, &templat); in vid_dec_mpeg12_Init()
82 priv->picture.base.profile = PIPE_VIDEO_PROFILE_MPEG2_MAIN; in vid_dec_mpeg12_Init()
83 priv->picture.mpeg12.intra_matrix = default_intra_matrix; in vid_dec_mpeg12_Init()
84 priv->picture.mpeg12.non_intra_matrix = default_non_intra_matrix; in vid_dec_mpeg12_Init()
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| D | vid_dec.c | 142 vid_dec_PrivateType *priv; in vid_dec_Constructor() local
150 priv = comp->pComponentPrivate = CALLOC(1, sizeof(vid_dec_PrivateType)); in vid_dec_Constructor()
151 if (!priv) in vid_dec_Constructor()
158 priv->profile = PIPE_VIDEO_PROFILE_UNKNOWN; in vid_dec_Constructor()
161 priv->profile = PIPE_VIDEO_PROFILE_MPEG2_MAIN; in vid_dec_Constructor()
164 priv->profile = PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH; in vid_dec_Constructor()
167 priv->profile = PIPE_VIDEO_PROFILE_HEVC_MAIN; in vid_dec_Constructor()
169 priv->BufferMgmtCallback = vid_dec_FrameDecoded; in vid_dec_Constructor()
170 priv->messageHandler = vid_dec_MessageHandler; in vid_dec_Constructor()
171 priv->destructor = vid_dec_Destructor; in vid_dec_Constructor()
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| D | vid_dec_h264.c | 84 static void vid_dec_h264_Decode(vid_dec_PrivateType *priv, struct vl_vlc *vlc, unsigned min_bits_le…
85 static void vid_dec_h264_EndFrame(vid_dec_PrivateType *priv);
86 static struct pipe_video_buffer *vid_dec_h264_Flush(vid_dec_PrivateType *priv, OMX_TICKS *timestamp…
88 void vid_dec_h264_Init(vid_dec_PrivateType *priv) in vid_dec_h264_Init() argument
90 priv->picture.base.profile = PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH; in vid_dec_h264_Init()
92 priv->Decode = vid_dec_h264_Decode; in vid_dec_h264_Init()
93 priv->EndFrame = vid_dec_h264_EndFrame; in vid_dec_h264_Init()
94 priv->Flush = vid_dec_h264_Flush; in vid_dec_h264_Init()
96 LIST_INITHEAD(&priv->codec_data.h264.dpb_list); in vid_dec_h264_Init()
97 priv->picture.h264.field_order_cnt[0] = priv->picture.h264.field_order_cnt[1] = INT_MAX; in vid_dec_h264_Init()
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| D | vid_enc.c | 148 vid_enc_PrivateType *priv; in vid_enc_Constructor() local
156 priv = comp->pComponentPrivate = CALLOC(1, sizeof(vid_enc_PrivateType)); in vid_enc_Constructor()
157 if (!priv) in vid_enc_Constructor()
164 priv->BufferMgmtCallback = vid_enc_BufferEncoded; in vid_enc_Constructor()
165 priv->messageHandler = vid_enc_MessageHandler; in vid_enc_Constructor()
166 priv->destructor = vid_enc_Destructor; in vid_enc_Constructor()
173 priv->screen = omx_get_screen(); in vid_enc_Constructor()
174 if (!priv->screen) in vid_enc_Constructor()
177 screen = priv->screen->pscreen; in vid_enc_Constructor()
182 priv->s_pipe = screen->context_create(screen, NULL, 0); in vid_enc_Constructor()
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| /external/u-boot/drivers/spi/ |
| D | designware_spi.c | 116 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset) in dw_read() argument
118 return __raw_readl(priv->regs + offset); in dw_read()
121 static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val) in dw_write() argument
123 __raw_writel(val, priv->regs + offset); in dw_write()
129 struct dw_spi_priv *priv = dev_get_priv(bus); in request_gpio_cs() local
133 ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0); in request_gpio_cs()
142 if (dm_gpio_is_valid(&priv->cs_gpio)) { in request_gpio_cs()
143 dm_gpio_set_dir_flags(&priv->cs_gpio, in request_gpio_cs()
169 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable) in spi_enable_chip() argument
171 dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0)); in spi_enable_chip()
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| D | omap3_spi.c | 122 static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val) in omap3_spi_write_chconf() argument
124 writel(val, &priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
126 readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
129 static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable) in omap3_spi_set_enable() argument
131 writel(enable, &priv->regs->channel[priv->cs].chctrl); in omap3_spi_set_enable()
133 readl(&priv->regs->channel[priv->cs].chctrl); in omap3_spi_set_enable()
136 static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len, in omap3_spi_write() argument
142 chconf = readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write()
145 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); in omap3_spi_write()
148 chconf |= (priv->wordlen - 1) << 7; in omap3_spi_write()
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| D | fsl_qspi.c | 142 struct fsl_qspi_priv priv; member
158 static inline int is_controller_busy(const struct fsl_qspi_priv *priv) in is_controller_busy() argument
166 val = qspi_read32(priv->flags, &priv->regs->sr); in is_controller_busy()
188 static void qspi_set_lut(struct fsl_qspi_priv *priv) in qspi_set_lut() argument
190 struct fsl_qspi_regs *regs = priv->regs; in qspi_set_lut()
194 qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE); in qspi_set_lut()
195 qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_UNLOCK); in qspi_set_lut()
199 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) | in qspi_set_lut()
201 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); in qspi_set_lut()
202 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); in qspi_set_lut()
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| D | zynq_qspi.c | 119 static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) in zynq_qspi_init_hw() argument
121 struct zynq_qspi_regs *regs = priv->regs; in zynq_qspi_init_hw()
161 struct zynq_qspi_priv *priv = dev_get_priv(bus); in zynq_qspi_probe() local
163 priv->regs = plat->regs; in zynq_qspi_probe()
164 priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH; in zynq_qspi_probe()
167 zynq_qspi_init_hw(priv); in zynq_qspi_probe()
178 static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size) in zynq_qspi_read_data() argument
183 data, (unsigned)(priv->rx_buf), size); in zynq_qspi_read_data()
185 if (priv->rx_buf) { in zynq_qspi_read_data()
188 *((u8 *)priv->rx_buf) = data; in zynq_qspi_read_data()
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| D | pic32_spi.c | 82 static inline void pic32_spi_enable(struct pic32_spi_priv *priv) in pic32_spi_enable() argument
84 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set); in pic32_spi_enable()
87 static inline void pic32_spi_disable(struct pic32_spi_priv *priv) in pic32_spi_disable() argument
89 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr); in pic32_spi_disable()
92 static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv) in pic32_spi_rx_fifo_level() argument
94 u32 sr = readl(&priv->regs->status.raw); in pic32_spi_rx_fifo_level()
99 static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv) in pic32_spi_tx_fifo_level() argument
101 u32 sr = readl(&priv->regs->status.raw); in pic32_spi_tx_fifo_level()
107 static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes) in pic32_tx_max() argument
111 tx_left = (priv->tx_end - priv->tx) / n_bytes; in pic32_tx_max()
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| D | ti_qspi.c | 116 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) in ti_spi_set_speed() argument
123 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; in ti_spi_set_speed()
132 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, in ti_spi_set_speed()
133 &priv->base->clk_ctrl); in ti_spi_set_speed()
135 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_spi_set_speed()
138 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) in ti_qspi_cs_deactivate() argument
140 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); in ti_qspi_cs_deactivate()
142 readl(&priv->base->cmd); in ti_qspi_cs_deactivate()
145 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) in __ti_qspi_set_mode() argument
147 priv->dc = 0; in __ti_qspi_set_mode()
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| D | fsl_dspi.c | 103 struct fsl_dspi_priv priv; member
132 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt) in dspi_halt() argument
136 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); in dspi_halt()
143 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); in dspi_halt()
146 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val) in fsl_dspi_init_mcr() argument
149 dspi_halt(priv, 1); in fsl_dspi_init_mcr()
151 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val); in fsl_dspi_init_mcr()
154 dspi_halt(priv, 0); in fsl_dspi_init_mcr()
156 priv->mcr_val = cfg_val; in fsl_dspi_init_mcr()
159 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv, in fsl_dspi_cfg_cs_active_state() argument
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| /external/u-boot/drivers/video/exynos/ |
| D | exynos_fb.c | 102 static void exynos_fimd_set_dualrgb(struct exynos_fb_priv *priv, bool enabled) in exynos_fimd_set_dualrgb() argument
104 struct exynos_fb *reg = priv->reg; in exynos_fimd_set_dualrgb()
112 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()
119 static void exynos_fimd_set_dp_clkcon(struct exynos_fb_priv *priv, in exynos_fimd_set_dp_clkcon() argument
122 struct exynos_fb *reg = priv->reg; in exynos_fimd_set_dp_clkcon()
131 static void exynos_fimd_set_par(struct exynos_fb_priv *priv, in exynos_fimd_set_par() argument
134 struct exynos_fb *reg = priv->reg; in exynos_fimd_set_par()
154 switch (priv->vl_bpix) { in exynos_fimd_set_par()
171 cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) | in exynos_fimd_set_par()
172 EXYNOS_VIDOSD_BOTTOM_Y(priv->vl_row - 1) | in exynos_fimd_set_par()
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| /external/u-boot/drivers/net/ |
| D | tsec.c | 67 static void tsec_configure_serdes(struct tsec_private *priv) in tsec_configure_serdes() argument
73 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), in tsec_configure_serdes()
75 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), in tsec_configure_serdes()
77 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), in tsec_configure_serdes()
107 struct tsec_private *priv = (struct tsec_private *)dev->priv; in tsec_mcast_addr() local
108 struct tsec __iomem *regs = priv->regs; in tsec_mcast_addr()
177 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) in adjust_link() argument
179 struct tsec __iomem *regs = priv->regs; in adjust_link()
237 struct tsec_private *priv = (struct tsec_private *)dev->priv; in tsec_send() local
238 struct tsec __iomem *regs = priv->regs; in tsec_send()
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| D | ethoc.c | 201 static inline u32 *ethoc_reg(struct ethoc *priv, size_t offset) in ethoc_reg() argument
203 return priv->iobase + offset; in ethoc_reg()
206 static inline u32 ethoc_read(struct ethoc *priv, size_t offset) in ethoc_read() argument
208 return readl(ethoc_reg(priv, offset)); in ethoc_read()
211 static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data) in ethoc_write() argument
213 writel(data, ethoc_reg(priv, offset)); in ethoc_write()
216 static inline void ethoc_read_bd(struct ethoc *priv, int index, in ethoc_read_bd() argument
220 bd->stat = ethoc_read(priv, offset + 0); in ethoc_read_bd()
221 bd->addr = ethoc_read(priv, offset + 4); in ethoc_read_bd()
224 static inline void ethoc_write_bd(struct ethoc *priv, int index, in ethoc_write_bd() argument
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| D | cpsw.c | 248 #define for_active_slave(slave, priv) \ argument
249 slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
250 #define for_each_slave(slave, priv) \ argument
251 for (slave = (priv)->slaves; slave != (priv)->slaves + \
252 (priv)->data.slaves; slave++)
338 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) in cpsw_ale_read() argument
342 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); in cpsw_ale_read()
345 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); in cpsw_ale_read()
350 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) in cpsw_ale_write() argument
355 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); in cpsw_ale_write()
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| D | sni_ave.c | 102 #define AVE_DESC_SIZE(priv, num) \ argument
103 ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \
163 int (*get_pinmode)(struct ave_private *priv);
166 static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry, in ave_desc_read() argument
172 if (priv->data->is_desc_64bit) { in ave_desc_read()
182 return readl(priv->iobase + addr); in ave_desc_read()
185 static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id, in ave_desc_read_cmdsts() argument
188 return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS); in ave_desc_read_cmdsts()
191 static void ave_desc_write(struct ave_private *priv, enum desc_id id, in ave_desc_write() argument
197 if (priv->data->is_desc_64bit) { in ave_desc_write()
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| D | zynq_gem.c | 188 static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, in phy_setup_op() argument
192 struct zynq_gem_regs *regs = priv->iobase; in phy_setup_op()
219 static int phyread(struct zynq_gem_priv *priv, u32 phy_addr, in phyread() argument
224 ret = phy_setup_op(priv, phy_addr, regnum, in phyread()
234 static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr, in phywrite() argument
240 return phy_setup_op(priv, phy_addr, regnum, in phywrite()
248 struct zynq_gem_priv *priv = dev->priv; in phy_detection() local
250 if (priv->phyaddr != -1) { in phy_detection()
251 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); in phy_detection()
256 priv->phyaddr); in phy_detection()
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| D | ep93xx_eth.c | 28 #define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
43 struct ep93xx_priv *priv = GET_PRIV(dev); in dump_dev() local
47 printf(" rx_dq.base %p\n", priv->rx_dq.base); in dump_dev()
48 printf(" rx_dq.current %p\n", priv->rx_dq.current); in dump_dev()
49 printf(" rx_dq.end %p\n", priv->rx_dq.end); in dump_dev()
50 printf(" rx_sq.base %p\n", priv->rx_sq.base); in dump_dev()
51 printf(" rx_sq.current %p\n", priv->rx_sq.current); in dump_dev()
52 printf(" rx_sq.end %p\n", priv->rx_sq.end); in dump_dev()
57 printf(" tx_dq.base %p\n", priv->tx_dq.base); in dump_dev()
58 printf(" tx_dq.current %p\n", priv->tx_dq.current); in dump_dev()
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| /external/u-boot/drivers/gpio/ |
| D | xilinx_gpio.c | 50 struct xilinx_gpio_priv *priv = NULL; in gpio_get_controller() local
53 priv = list_entry(entry, struct xilinx_gpio_priv, list); in gpio_get_controller()
54 if (gpio >= priv->gpio_min && gpio <= priv->gpio_max) { in gpio_get_controller()
56 (u32)priv->regs, priv->gpio_min, priv->gpio_max); in gpio_get_controller()
57 return priv; in gpio_get_controller()
68 struct xilinx_gpio_priv *priv; in get_name() local
72 priv = gpio_get_controller(gpio); in get_name()
73 if (priv) { in get_name()
74 gpio_priv = gpio - priv->gpio_min; in get_name()
76 return *priv->gpio_name[gpio_priv].name ? in get_name()
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| /external/wpa_supplicant_8/wpa_supplicant/dbus/ |
| D | dbus_common.c | 58 static void process_watch(struct wpas_dbus_priv *priv, in process_watch() argument
61 dbus_connection_ref(priv->con); in process_watch()
63 priv->should_dispatch = 0; in process_watch()
72 if (priv->should_dispatch) { in process_watch()
73 dispatch_data(priv->con); in process_watch()
74 priv->should_dispatch = 0; in process_watch()
77 dbus_connection_unref(priv->con); in process_watch()
101 struct wpas_dbus_priv *priv = data; in add_watch() local
112 priv, watch); in add_watch()
116 priv, watch); in add_watch()
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| /external/u-boot/drivers/video/ |
| D | vidconsole-uclass.c | 71 struct vidconsole_priv *priv = dev_get_uclass_priv(dev); in vidconsole_back() local
81 priv->xcur_frac -= VID_TO_POS(priv->x_charsize); in vidconsole_back()
82 if (priv->xcur_frac < priv->xstart_frac) { in vidconsole_back()
83 priv->xcur_frac = (priv->cols - 1) * in vidconsole_back()
84 VID_TO_POS(priv->x_charsize); in vidconsole_back()
85 priv->ycur -= priv->y_charsize; in vidconsole_back()
86 if (priv->ycur < 0) in vidconsole_back()
87 priv->ycur = 0; in vidconsole_back()
97 struct vidconsole_priv *priv = dev_get_uclass_priv(dev); in vidconsole_newline() local
103 priv->xcur_frac = priv->xstart_frac; in vidconsole_newline()
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| /external/u-boot/drivers/mmc/ |
| D | tmio-common.c | 24 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg) in tmio_sd_readq() argument
26 return readq(priv->regbase + (reg << 1)); in tmio_sd_readq()
29 static void tmio_sd_writeq(struct tmio_sd_priv *priv, in tmio_sd_writeq() argument
32 writeq(val, priv->regbase + (reg << 1)); in tmio_sd_writeq()
35 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg) in tmio_sd_readw() argument
37 return readw(priv->regbase + (reg >> 1)); in tmio_sd_readw()
40 static void tmio_sd_writew(struct tmio_sd_priv *priv, in tmio_sd_writew() argument
43 writew(val, priv->regbase + (reg >> 1)); in tmio_sd_writew()
46 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg) in tmio_sd_readl() argument
50 if (priv->caps & TMIO_SD_CAP_64BIT) in tmio_sd_readl()
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| /external/u-boot/arch/sandbox/cpu/ |
| D | eth-raw-os.c | 29 struct eth_sandbox_raw_priv *priv) in _raw_packet_start() argument
37 priv->device = malloc(sizeof(struct sockaddr_ll)); in _raw_packet_start()
38 if (priv->device == NULL) in _raw_packet_start()
40 device = priv->device; in _raw_packet_start()
48 priv->sd = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL)); in _raw_packet_start()
49 if (priv->sd < 0) { in _raw_packet_start()
55 ret = setsockopt(priv->sd, SOL_SOCKET, SO_BINDTODEVICE, ifname, in _raw_packet_start()
64 flags = fcntl(priv->sd, F_GETFL, 0); in _raw_packet_start()
65 fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); in _raw_packet_start()
70 ret = setsockopt(priv->sd, SOL_PACKET, PACKET_ADD_MEMBERSHIP, in _raw_packet_start()
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| /external/u-boot/drivers/adc/ |
| D | meson-saradc.c | 181 meson_saradc_get_fifo_count(struct meson_saradc_priv *priv) in meson_saradc_get_fifo_count() argument
185 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_saradc_get_fifo_count()
190 static int meson_saradc_lock(struct meson_saradc_priv *priv) in meson_saradc_lock() argument
195 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_saradc_lock()
204 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); in meson_saradc_lock()
215 static void meson_saradc_unlock(struct meson_saradc_priv *priv) in meson_saradc_unlock() argument
218 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_saradc_unlock()
222 static void meson_saradc_clear_fifo(struct meson_saradc_priv *priv) in meson_saradc_clear_fifo() argument
227 if (!meson_saradc_get_fifo_count(priv)) in meson_saradc_clear_fifo()
230 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp); in meson_saradc_clear_fifo()
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| /external/libpcap/ |
| D | pcap-rdmasniff.c | 68 struct pcap_rdmasniff *priv = handle->priv; in rdmasniff_stats() local
70 stat->ps_recv = priv->packets_recv; in rdmasniff_stats()
80 struct pcap_rdmasniff *priv = handle->priv; in rdmasniff_cleanup() local
82 ibv_dereg_mr(priv->mr); in rdmasniff_cleanup()
83 ibv_destroy_flow(priv->flow); in rdmasniff_cleanup()
84 ibv_destroy_qp(priv->qp); in rdmasniff_cleanup()
85 ibv_destroy_cq(priv->cq); in rdmasniff_cleanup()
86 ibv_dealloc_pd(priv->pd); in rdmasniff_cleanup()
87 ibv_destroy_comp_channel(priv->channel); in rdmasniff_cleanup()
88 ibv_close_device(priv->context); in rdmasniff_cleanup()
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