| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 335 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) { in regsOverlap() local
336 if (*regList == regB) return true; in regsOverlap()
350 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ in isSuperRegister() local
351 if (*regList == regB) return true; in isSuperRegister()
|
| D | TargetCallingConv.td | 71 class CCAssignToReg<list<Register> regList> : CCAction {
72 list<Register> RegList = regList;
77 class CCAssignToRegWithShadow<list<Register> regList,
79 list<Register> RegList = regList;
|
| D | Target.td | 107 dag regList, RegAltNameIndex idx = NoRegAltName> {
137 dag MemberList = regList;
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.td | 20 class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>
21 : RegisterClass<"WebAssembly", regTypes, alignment, regList>;
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.td | 18 class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
19 : RegisterClass <"NVPTX", regTypes, alignment, regList>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.td | 20 class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>
21 : RegisterClass<"WebAssembly", regTypes, alignment, regList>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetCallingConv.td | 89 class CCAssignToReg<list<Register> regList> : CCAction {
90 list<Register> RegList = regList;
95 class CCAssignToRegWithShadow<list<Register> regList,
97 list<Register> RegList = regList;
|
| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.td | 89 class CCAssignToReg<list<Register> regList> : CCAction {
90 list<Register> RegList = regList;
95 class CCAssignToRegWithShadow<list<Register> regList,
97 list<Register> RegList = regList;
|
| /external/swiftshader/third_party/LLVM/test/TableGen/ |
| D | Slice.td | 36 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
38 list<Register> MemberList = regList;
|
| D | cast.td | 36 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
38 list<Register> MemberList = regList;
|
| D | TargetInstrSpec.td | 37 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
39 list<Register> MemberList = regList;
|
| D | MultiPat.td | 45 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
47 list<Register> MemberList = regList;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.td | 18 class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
19 : RegisterClass <"NVPTX", regTypes, alignment, regList>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
| D | TargetInstrSpec.td | 42 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
44 list<Register> MemberList = regList;
|
| D | cast.td | 41 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
43 list<Register> MemberList = regList;
|
| D | Slice.td | 35 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
37 list<Register> MemberList = regList;
|
| D | MultiPat.td | 45 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
47 list<Register> MemberList = regList;
|
| /external/llvm/test/TableGen/ |
| D | TargetInstrSpec.td | 42 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
44 list<Register> MemberList = regList;
|
| D | cast.td | 41 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
43 list<Register> MemberList = regList;
|
| D | Slice.td | 35 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
37 list<Register> MemberList = regList;
|
| D | MultiPat.td | 45 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
47 list<Register> MemberList = regList;
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 39 dag regList> {
45 def Bit : RegisterClass<"SystemZ", types, size, regList> {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 39 dag regList, bit allocatable = 1> {
46 def Bit : RegisterClass<"SystemZ", types, size, regList> {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 484 list<ValueType> regTypes, int alignment, dag regList> {
494 dag MemberList = regList;
521 * The final argument, ``regList``, specifies which registers are in this class.
522 If an alternative allocation order method is not specified, then ``regList``
|
| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 484 list<ValueType> regTypes, int alignment, dag regList> {
494 dag MemberList = regList;
521 * The final argument, ``regList``, specifies which registers are in this class.
522 If an alternative allocation order method is not specified, then ``regList``
|