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/external/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s12 # CHECK-EL: sra $4, $3, 7 # encoding: [0x83,0x00,0x80,0x38]
25 # CHECK-EL: sra $3, $3, 7 # encoding: [0x63,0x00,0x80,0x38]
32 # CHECK-EB: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80]
45 # CHECK-EB: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
49 sra $4, $3, 7
56 sra $2, $3, $5
59 sra $2, $3
62 sra $3, 7
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s12 # CHECK-EL: sra $4, $3, 7 # encoding: [0x83,0x00,0x80,0x38]
25 # CHECK-EL: sra $3, $3, 7 # encoding: [0x63,0x00,0x80,0x38]
32 # CHECK-EB: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80]
45 # CHECK-EB: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
49 sra $4, $3, 7
56 sra $2, $3, $5
59 sra $2, $3
62 sra $3, 7
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dshift-03.ll8 ; CHECK: sra %r2, 1
17 ; CHECK: sra %r2, 31
26 ; CHECK-NOT: sra %r2, 32
35 ; CHECK-NOT: sra %r2, -1{{.*}}
45 ; CHECK: sra %r2, 0(%r3)
54 ; CHECK: sra %r2, 10(%r3)
64 ; CHECK: sra %r2, 10(%r3)
76 ; CHECK: sra %r2, 4095(%r3)
87 ; CHECK: sra %r2, 0(%r3)
98 ; CHECK: sra %r2, 0({{%r[34]}})
[all …]
Dselectcc-01.ll10 ; CHECK-NEXT: sra %r2, 31
23 ; CHECK-NEXT: sra %r2, 31
35 ; CHECK-NEXT: sra %r2, 31
48 ; CHECK-NEXT: sra %r2, 31
61 ; CHECK-NEXT: sra %r2, 31
74 ; CHECK-NEXT: sra %r2, 31
86 ; CHECK-NEXT: sra %r2, 31
98 ; CHECK-NEXT: sra %r2, 31
111 ; CHECK-NEXT: sra %r2, 31
123 ; CHECK-NEXT: sra %r2, 31
[all …]
Dselectcc-02.ll10 ; CHECK-NEXT: sra %r2, 31
23 ; CHECK-NEXT: sra %r2, 31
35 ; CHECK-NEXT: sra %r2, 31
48 ; CHECK-NEXT: sra %r2, 31
60 ; CHECK-NEXT: sra %r2, 31
73 ; CHECK-NEXT: sra %r2, 31
85 ; CHECK-NEXT: sra %r2, 31
97 ; CHECK-NEXT: sra %r2, 31
110 ; CHECK-NEXT: sra %r2, 31
123 ; CHECK-NEXT: sra %r2, 31
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dshift-03.ll8 ; CHECK: sra %r2, 1
17 ; CHECK: sra %r2, 31
26 ; CHECK-NOT: sra %r2, 32
35 ; CHECK-NOT: sra %r2, -1{{.*}}
45 ; CHECK: sra %r2, 0(%r3)
54 ; CHECK: sra %r2, 10(%r3)
64 ; CHECK: sra %r2, 10(%r3)
76 ; CHECK: sra %r2, 4095(%r3)
87 ; CHECK: sra %r2, 0(%r3)
98 ; CHECK: sra %r2, 0({{%r[34]}})
[all …]
Dselectcc-02.ll10 ; CHECK-NEXT: sra %r2, 31
23 ; CHECK-NEXT: sra %r2, 31
35 ; CHECK-NEXT: sra %r2, 31
48 ; CHECK-NEXT: sra %r2, 31
60 ; CHECK-NEXT: sra %r2, 31
73 ; CHECK-NEXT: sra %r2, 31
85 ; CHECK-NEXT: sra %r2, 31
97 ; CHECK-NEXT: sra %r2, 31
110 ; CHECK-NEXT: sra %r2, 31
123 ; CHECK-NEXT: sra %r2, 31
[all …]
Dselectcc-01.ll10 ; CHECK-NEXT: sra %r2, 31
23 ; CHECK-NEXT: sra %r2, 31
35 ; CHECK-NEXT: sra %r2, 31
48 ; CHECK-NEXT: sra %r2, 31
61 ; CHECK-NEXT: sra %r2, 31
74 ; CHECK-NEXT: sra %r2, 31
86 ; CHECK-NEXT: sra %r2, 31
98 ; CHECK-NEXT: sra %r2, 31
111 ; CHECK-NEXT: sra %r2, 31
123 ; CHECK-NEXT: sra %r2, 31
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dmul.ll39 ; M2: sra $2, $[[T0]], 31
43 ; 32R1-R5: sra $2, $[[T0]], 31
47 ; 32R6: sra $2, $[[T0]], 31
52 ; M4: sra $2, $[[T0]], 31
56 ; 64R1-R5: sra $2, $[[T0]], 31
60 ; 64R6: sra $2, $[[T0]], 31
64 ; MM32: sra $2, $[[T0]], 31
77 ; M2: sra $2, $[[T0]], 24
81 ; 32R1: sra $2, $[[T0]], 24
92 ; M4: sra $2, $[[T0]], 24
[all …]
Dsdiv.ll43 ; FIXME: The sll/sra instructions are redundant since div is signed.
45 ; NOT-R6: sra $2, $[[T1]], 31
49 ; FIXME: The sll/sra instructions are redundant since div is signed.
51 ; R6: sra $2, $[[T1]], 31
57 ; MMR3: sra $2, $[[T1]], 31
62 ; MMR6: sra $2, $[[T1]], 31
75 ; FIXME: The sll/sra instructions are redundant since div is signed.
77 ; NOT-R2-R6: sra $2, $[[T1]], 24
110 ; FIXME: The sll/sra instructions are redundant since div is signed.
112 ; NOT-R2-R6: sra $2, $[[T1]], 16
Dadd.ll40 ; NOT-R2-R6: sra $2, $[[T0]], 31
44 ; R2-R6: sra $2, $[[T0]], 31
48 ; MMR6: sra $2, $[[T1]], 31
60 ; NOT-R2-R6: sra $2, $[[T0]], 24
78 ; NOT-R2-R6: sra $2, $[[T0]], 16
192 ; NOT-R2-R6: sra $2, $[[T0]], 24
213 ; NOT-R2-R6: sra $2, $[[T0]], 16
311 ; GP32: sra $[[T1]], $[[T0]], 31
314 ; GP64: sra $[[T1]], $[[T0]], 31
317 ; MMR6: sra $[[T0]], $[[T0]], 31
[all …]
Dsrem.ll44 ; NOT-R6: sra $2, $[[T1]], 31
49 ; R6: sra $2, $[[T3]], 31
55 ; MMR3: sra $2, $[[T1]], 31
60 ; MMR6: sra $2, $[[T1]], 31
74 ; NOT-R2-R6: sra $2, $[[T1]], 24
106 ; NOT-R2-R6: sra $2, $[[T1]], 16
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/
Dcallabi.ll16 ; 32R1: sra $4, $[[T1]], 24
31 ; 32R1: sra $4, $[[T1]], 16
59 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24
61 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
78 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 16
80 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16
111 ; 32R1-DAG: sra $4, $[[T3]], 24
113 ; 32R1-DAG: sra $5, $[[T4]], 24
115 ; 32R1-DAG: sra $6, $[[T5]], 24
134 ; 32R1-DAG: sra $4, $[[T3]], 16
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dcallabi.ll16 ; 32R1: sra $4, $[[T1]], 24
31 ; 32R1: sra $4, $[[T1]], 16
59 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24
61 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
78 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 16
80 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16
111 ; 32R1-DAG: sra $4, $[[T3]], 24
113 ; 32R1-DAG: sra $5, $[[T4]], 24
115 ; 32R1-DAG: sra $6, $[[T5]], 24
134 ; 32R1-DAG: sra $4, $[[T3]], 16
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dcombine-sra.ll6 ; fold (sra 0, x) -> 0
21 ; fold (sra -1, x) -> -1
36 ; fold (sra x, c >= size(x)) -> undef
53 ; fold (sra x, 0) -> x
62 ; fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
147 ; fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
193 ; fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
233 ; fold (sra (trunc (sra x, c1)), c2) -> (trunc (sra x, c1 + c2))
Dsse2-vector-shifts.ll277 %sra = ashr <4 x i32> %x, %y
278 %srl1 = lshr <4 x i32> %sra, <i32 31, i32 31, i32 31, i32 31>
332 %sra = ashr <4 x i16> %trunc, <i16 3, i16 3, i16 3, i16 3>
333 ret <4 x i16> %sra
352 %sra = ashr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
353 ret <4 x i32> %sra
361 %sra = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
362 ret <4 x i32> %sra
370 %sra = shl <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
371 ret <4 x i32> %sra
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-mips.ll66 ; MIPS32: sra a0,a0,0x18
78 ; MIPS32: sra a3,a3,0x18
90 ; MIPS32: sra a0,a0,0x10
102 ; MIPS32: sra a3,a3,0x10
114 ; MIPS32: sra a0,a0,0x1f
126 ; MIPS32: sra a2,a2,0x1f
139 ; MIPS32: sra a0,a0,0x1f
152 ; MIPS32: sra a3,a3,0x1f
165 ; MIPS32: sra a0,a0,0x1f
178 ; MIPS32: sra a3,a3,0x1f
Dvector-cast.ll40 ; MIPS32: sra t2,t2,0x1f
50 ; MIPS32: sra v0,v0,0x1f
62 ; MIPS32: sra t2,t2,0x1f
72 ; MIPS32: sra a0,a0,0x1f
81 ; MIPS32: sra v0,v0,0x1f
91 ; MIPS32: sra v1,v1,0x1f
103 ; MIPS32: sra v0,v0,0x1f
113 ; MIPS32: sra a1,a1,0x1f
122 ; MIPS32: sra v0,v0,0x1f
132 ; MIPS32: sra v1,v1,0x1f
[all …]
Dtest_i1.ll190 ; MIPS32: sra {{.*}},0x1f
192 ; MIPS32: sra {{.*}},0x18
219 ; MIPS32: sra {{.*}},0x1f
221 ; MIPS32: sra {{.*}},0x10
246 ; MIPS32: sra {{.*}},0x1f
272 ; MIPS32: sra {{.*}},0x1f
296 ; MIPS32: sra {{.*}},0x1f
329 ; MIPS32: sra {{.*}},0x1f
348 ; MIPS32: sra {{.*}},0x1f
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
Darithmetic.td11 // CHECK: bits<8> sra = { 0, 0, 0, 1, 1, 1, 1, 1 };
21 bits<8> sra = !sra(a, b);
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dshift-dagcombine.ll8 ; CHECK-NOT: sra
10 ; CHECK-NOT: sra
16 ; CHECK-NOT: sra
18 ; CHECK-NOT: sra
/external/llvm/test/CodeGen/Mips/msa/
Dshift-dagcombine.ll8 ; CHECK-NOT: sra
10 ; CHECK-NOT: sra
16 ; CHECK-NOT: sra
18 ; CHECK-NOT: sra
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/
Dmul.ll76 ; M2: sra $2, $[[T0]], 24
80 ; 32R1: sra $2, $[[T0]], 24
91 ; M4: sra $2, $[[T0]], 24
95 ; 64R1: sra $2, $[[T0]], 24
117 ; M2: sra $2, $[[T0]], 16
121 ; 32R1: sra $2, $[[T0]], 16
132 ; M4: sra $2, $[[T0]], 16
136 ; 64R1: sra $2, $[[T0]], 16
/external/freetype/src/tools/
Dtest_trig.c198 double ra, cra, sra; in test_rotate() local
204 sra = sin( ra ); in test_rotate()
224 c3 = c1 * cra - s1 * sra; in test_rotate()
225 s3 = c1 * sra + s1 * cra; in test_rotate()
/external/llvm/test/CodeGen/X86/
Dsse2-vector-shifts.ll277 %sra = ashr <4 x i32> %x, %y
278 %srl1 = lshr <4 x i32> %sra, <i32 31, i32 31, i32 31, i32 31>
332 %sra = ashr <4 x i16> %trunc, <i16 3, i16 3, i16 3, i16 3>
333 ret <4 x i16> %sra
353 %sra = ashr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
354 ret <4 x i32> %sra
362 %sra = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
363 ret <4 x i32> %sra
371 %sra = shl <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
372 ret <4 x i32> %sra

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