DPR (reference) in projects: external - OpenGrok search results

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Searched refs:DPR (Results 1 – 25 of 26) sorted by relevance

/external/llvm/lib/Target/ARM/
D	ARMInstrVFP.td	101 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 103 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>; 120 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 122 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>; 337 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 339 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; 359 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 361 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; 381 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 383 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; [all …]
D	ARMInstrNEON.td	139 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> { 157 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> { 166 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> { 184 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> { 193 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> { 203 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> { 232 def VecListThreeDAllLanes : RegisterOperand<DPR, 242 def VecListThreeQAllLanes : RegisterOperand<DPR, 252 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> { 261 def VecListFourQAllLanes : RegisterOperand<DPR, [all …]
D	ARMRegisterInfo.td	`291 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64, 295 let AltOrders = [(rotl DPR, 16), 296 (add (decimate (rotl DPR, 16), 2), (rotl DPR, 16))]; 302 // Subset of DPR that are accessible with VFP2 (and so that also have 305 (trunc DPR, 16)>; 307 // Subset of DPR which can be used as a source of NEON scalars for 16-bit 310 (trunc DPR, 8)>; 333 [(decimate (shl DPR, 1), 2), 334 (decimate (shl DPR, 2), 2)]>; 359 [(shl DPR, 0), [all …]`
D	README.txt	`170 before the call and place the result in a callee-save DPR register. The two`
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
D	ARMInstrVFP.td	71 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 73 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; 85 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 87 [(store (f64 DPR:$Dd), addrmode5:$addr)]>; 201 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 203 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; 215 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 217 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; 229 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 231 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; [all …]
D	ARMInstrNEON.td	218 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd), 226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2), 251 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb), 259 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), 284 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), 292 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), 314 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), 323 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), 346 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), 355 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), [all …]
D	ARMRegisterInfo.td	`275 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, 278 let AltOrders = [(rotl DPR, 16)]; 282 // Subset of DPR that are accessible with VFP2 (and so that also have 285 (trunc DPR, 16)> { 289 // Subset of DPR which can be used as a source of NEON scalars for 16-bit 292 (trunc DPR, 8)> { 299 let SubRegClasses = [(DPR dsub_0, dsub_1)]; 322 let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3), 340 let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3,`
D	README.txt	`170 before the call and place the result in a callee-save DPR register. The two`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
D	ARMInstrVFP.td	121 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 123 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>; 140 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 142 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>; 337 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 339 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>, 362 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 364 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>, 387 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 389 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>, [all …]
D	ARMInstrNEON.td	129 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> { 147 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> { 156 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> { 174 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> { 183 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> { 193 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> { 222 def VecListThreeDAllLanes : RegisterOperand<DPR, 232 def VecListThreeQAllLanes : RegisterOperand<DPR, 242 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> { 251 def VecListFourQAllLanes : RegisterOperand<DPR, [all …]
D	ARMRegisterInfo.td	`332 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64, 336 let AltOrders = [(rotl DPR, 16), 337 (add (decimate (rotl DPR, 16), 2), (rotl DPR, 16))]; 341 let DiagnosticType = "DPR"; 344 // Subset of DPR that are accessible with VFP2 (and so that also have 347 (trunc DPR, 16)> { 351 // Subset of DPR which can be used as a source of NEON scalars for 16-bit 354 (trunc DPR, 8)> { 384 [(decimate (shl DPR, 1), 2), 385 (decimate (shl DPR, 2), 2)]>; [all …]`
D	ARMRegisterBanks.td	`14 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;`
D	README.txt	`170 before the call and place the result in a callee-save DPR register. The two`
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
D	ARMGenDAGISel.inc	1225 …} (and:{ :[v2i32] } DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vd), (and:{ :[v2i32] } DPR:{ :[v2… 1226 … // Dst: (VBSLd:{ :[v2i32] } DPR:{ :[v2i32] }:$Vd, DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm) 1233 …} (and:{ :[v1i64] } DPR:{ :[v1i64] }:$Vn, DPR:{ :[v1i64] }:$Vd), (and:{ :[v1i64] } DPR:{ :[v1… 1234 … // Dst: (VBSLd:{ :[v1i64] } DPR:{ :[v1i64] }:$Vd, DPR:{ :[v1i64] }:$Vn, DPR:{ :[v1i64] }:$Vm) 1280 …DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vd), (and:{ :[v2i32] } DPR:{ :[v2i32] }:$Vm, (xor:{ :… 1281 … // Dst: (VBSLd:{ :[v2i32] } DPR:{ :[v2i32] }:$Vd, DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm) 1308 …DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vd), (and:{ :[v2i32] } (xor:{ :[v2i32] } DPR:{ :[v2i3… 1309 … // Dst: (VBSLd:{ :[v2i32] } DPR:{ :[v2i32] }:$Vd, DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm) 1332 …DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vd), (and:{ :[v2i32] } (xor:{ :[v2i32] } (bitconvert:{… 1333 … // Dst: (VBSLd:{ :[v2i32] } DPR:{ :[v2i32] }:$Vd, DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm) [all …]
D	ARMGenGlobalISel.inc	1389 …// (add:{ :[v1i64] } DPR:{ :[v1i64] }:$Vn, DPR:{ :[v1i64] }:$Vm) => (VADDv1i64:{ :[v1i64] } … 1419 …DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm), DPR:{ :[v2i32] }:$src1) => (VABAsv2i32:{ :[v2i3… 1444 …DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm), DPR:{ :[v2i32] }:$src1) => (VABAuv2i32:{ :[v2i3… 1469 …DPR:{ :[v2i32] }:$src1, (intrinsic_wo_chain:{ :[v2i32] } 1016:{ :[iPTR] }, DPR:{ :[v2i32] }:$V… 1494 …DPR:{ :[v2i32] }:$src1, (intrinsic_wo_chain:{ :[v2i32] } 1017:{ :[iPTR] }, DPR:{ :[v2i32] }:$V… 1517 …DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm), DPR:{ :[v2i32] }:$src1) => (VMLAv2i32:{ :[v2i32… 1540 …DPR:{ :[v2i32] }:$src1, (mul:{ :[v2i32] } DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm)) => (V… 1557 …// (add:{ :[v2i32] } DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm) => (VADDv2i32:{ :[v2i32] } … 1593 …DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm)), QPR:{ :[v2i64] }:$src1) => (VABALsv2i64:{ :[v2… 1622 …DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm)), QPR:{ :[v2i64] }:$src1) => (VABALuv2i64:{ :[v2… [all …]
D	ARMGenRegisterInfo.inc	`1692 // DPR Register Class... 1693 const MCPhysReg DPR[] = { 1697 // DPR Bit set. 2653 { DPR, DPRBits, 1422, 32, sizeof(DPRBits), ARM::DPRRegClassID, 8, 1, true }, 3541 { 64, 64, 64, VTLists+12 }, // DPR 8495 { // DPR 13456 {2, 64}, // DPR 13584 "DPR", 13614 64, // 20: DPR`
D	ARMGenAsmMatcher.inc	`4399 MCK_DPR, // register class 'DPR'`
/external/capstone/arch/ARM/
D	ARMGenAsmWriter.inc	8790 // (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p) 9339 // (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p) 9350 // (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p) 9387 // (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p) 9398 // (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p) 9435 // (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p) 9461 // (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) 9500 // (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) 9513 // (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) 9552 // (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) [all …]
D	ARMGenRegisterInfo.inc	`1328 // DPR Register Class... 1329 static uint16_t DPR[] = { 1333 // DPR Bit set. 2194 { "DPR", DPR, DPRBits, 32, sizeof(DPRBits), ARM_DPRRegClassID, 8, 8, 1, 1 },`
/external/u-boot/arch/x86/include/asm/arch-broadwell/
D	pch.h	`53 #define DPR 0x5c macro`
/external/llvm/test/CodeGen/ARM/
D	integer_insertelement.ll	`5 ; one DPR to another that we check for.`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
D	integer_insertelement.ll	`5 ; one DPR to another that we check for.`
/external/u-boot/arch/x86/cpu/broadwell/
D	sdram.c	`139 dm_pci_read_config32(dev, DPR, &dpr); in get_top_of_ram()`
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D	2013-1_UNLOCODE_CodeListPart3.csv	`8665 ,"TR","DPR","Dumlupinar","Dumlupinar","43","0-------","RN","9710",,, 13755 "+","US","DPR","Des Peres","Des Peres","MO","--3-----","RL","1301",,"3836N 09025W",`
D	2013-1_UNLOCODE_CodeListPart2.csv	`9357 "#","IN","DPR","Dappar","Dappar","PB","--3--6--","AA","1301",,"3031N 07648E","@Fun@Sta@Coo"`

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