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Searched refs:out_be32 (Results 1 – 25 of 173) sorted by relevance

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/external/u-boot/board/freescale/m54418twr/
Dm54418twr.c57 out_be32(&sdram->rcrcr, 0x40000000); in dram_init()
58 out_be32(&sdram->padcr, 0x01030203); in dram_init()
60 out_be32(&sdram->cr00, 0x01010101); in dram_init()
61 out_be32(&sdram->cr01, 0x00000101); in dram_init()
62 out_be32(&sdram->cr02, 0x01010100); in dram_init()
63 out_be32(&sdram->cr03, 0x01010000); in dram_init()
64 out_be32(&sdram->cr04, 0x00010101); in dram_init()
65 out_be32(&sdram->cr06, 0x00010100); in dram_init()
66 out_be32(&sdram->cr07, 0x00000001); in dram_init()
67 out_be32(&sdram->cr08, 0x01000001); in dram_init()
[all …]
/external/u-boot/drivers/ddr/fsl/
Dmpc85xx_ddr_gen3.c70 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
93 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
94 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
95 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
98 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
99 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
100 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
103 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
104 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
105 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
[all …]
Dfsl_mmdc.c18 out_be32(ptr, value); in set_wait_for_bits_clear()
34 out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ); in mmdc_init()
37 out_be32(&mmdc->mdotc, priv->mdotc); in mmdc_init()
38 out_be32(&mmdc->mdcfg0, priv->mdcfg0); in mmdc_init()
39 out_be32(&mmdc->mdcfg1, priv->mdcfg1); in mmdc_init()
40 out_be32(&mmdc->mdcfg2, priv->mdcfg2); in mmdc_init()
43 out_be32(&mmdc->mdmisc, priv->mdmisc); in mmdc_init()
44 out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR); in mmdc_init()
45 out_be32(&mmdc->mdrwd, priv->mdrwd); in mmdc_init()
46 out_be32(&mmdc->mpodtctrl, priv->mpodtctrl); in mmdc_init()
[all …]
Dmpc85xx_ddr_gen2.c41 out_be32(&gur->ddrioovcr, 0x90000000); in fsl_ddr_set_memctl_regs()
43 out_be32(&gur->ddrioovcr, 0xA8000000); in fsl_ddr_set_memctl_regs()
49 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
50 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
53 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
57 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
58 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
61 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
[all …]
Dmpc86xx_ddr.c34 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
46 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
47 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
51 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
52 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
[all …]
/external/u-boot/arch/m68k/cpu/mcf532x/
Dcpu_init.c29 out_be32(&scm1->mpr, 0x77777777); in cpu_init_f()
30 out_be32(&scm1->pacra, 0); in cpu_init_f()
31 out_be32(&scm1->pacrb, 0); in cpu_init_f()
32 out_be32(&scm1->pacrc, 0); in cpu_init_f()
33 out_be32(&scm1->pacrd, 0); in cpu_init_f()
34 out_be32(&scm1->pacre, 0); in cpu_init_f()
35 out_be32(&scm1->pacrf, 0); in cpu_init_f()
36 out_be32(&scm1->pacrg, 0); in cpu_init_f()
41 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); in cpu_init_f()
42 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); in cpu_init_f()
[all …]
/external/u-boot/board/sbc8548/
Dddr.c94 out_be32(&ddr->cs0_bnds, 0x0000007f); in fixed_sdram()
95 out_be32(&ddr->cs1_bnds, 0x008000ff); in fixed_sdram()
96 out_be32(&ddr->cs2_bnds, 0x00000000); in fixed_sdram()
97 out_be32(&ddr->cs3_bnds, 0x00000000); in fixed_sdram()
99 out_be32(&ddr->cs0_config, 0x80010101); in fixed_sdram()
100 out_be32(&ddr->cs1_config, 0x80010101); in fixed_sdram()
101 out_be32(&ddr->cs2_config, 0x00000000); in fixed_sdram()
102 out_be32(&ddr->cs3_config, 0x00000000); in fixed_sdram()
104 out_be32(&ddr->timing_cfg_3, 0x00000000); in fixed_sdram()
105 out_be32(&ddr->timing_cfg_0, 0x00220802); in fixed_sdram()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc8xx/
Dcpu_init.c30 out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); in cpu_init_f()
40 out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY); in cpu_init_f()
44 out_be32(&immr->im_sitk.sitk_tbk, KAPWR_KEY); in cpu_init_f()
48 out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY); in cpu_init_f()
53 out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY); in cpu_init_f()
79 out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY); in cpu_init_f()
90 out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR); in cpu_init_f()
128 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP); in cpu_init_f()
131 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP); in cpu_init_f()
134 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP); in cpu_init_f()
[all …]
/external/u-boot/arch/m68k/cpu/mcf5227x/
Dcpu_init.c36 out_be32(&pll->psr, 0x12); in cpu_init_f()
38 out_be32(&scm1->mpr, 0x77777777); in cpu_init_f()
39 out_be32(&scm1->pacra, 0); in cpu_init_f()
40 out_be32(&scm1->pacrb, 0); in cpu_init_f()
41 out_be32(&scm1->pacrc, 0); in cpu_init_f()
42 out_be32(&scm1->pacrd, 0); in cpu_init_f()
43 out_be32(&scm1->pacre, 0); in cpu_init_f()
44 out_be32(&scm1->pacrf, 0); in cpu_init_f()
45 out_be32(&scm1->pacrg, 0); in cpu_init_f()
46 out_be32(&scm1->pacri, 0); in cpu_init_f()
[all …]
/external/u-boot/arch/m68k/cpu/mcf547x_8x/
Dcpu_init.c35 out_be32(&xlbarb->adrto, 0x2000); in cpu_init_f()
36 out_be32(&xlbarb->datto, 0x2500); in cpu_init_f()
37 out_be32(&xlbarb->busto, 0x3000); in cpu_init_f()
39 out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT); in cpu_init_f()
42 out_be32(&xlbarb->prien, 0xff); in cpu_init_f()
43 out_be32(&xlbarb->pri, 0); in cpu_init_f()
46 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); in cpu_init_f()
47 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); in cpu_init_f()
48 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); in cpu_init_f()
52 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); in cpu_init_f()
[all …]
Dpci.c31 out_be32(hose->cfg_addr, addr); \
35 out_be32(hose->cfg_addr, addr & 0x7fffffff); \
53 out_be32(hose->cfg_addr, addr); in pci_read_cfg_dword()
56 out_be32(hose->cfg_addr, addr & 0x7fffffff); in pci_read_cfg_dword()
61 out_be32(hose->cfg_addr, addr); in pci_read_cfg_dword()
64 out_be32(hose->cfg_addr, addr & 0x7fffffff); in pci_read_cfg_dword()
90 out_be32(&pci->tcr1, PCI_TCR1_P); in pci_mcf547x_8x_init()
93 out_be32(&pci->iw0btar, in pci_mcf547x_8x_init()
95 out_be32(&pci->iw1btar, in pci_mcf547x_8x_init()
97 out_be32(&pci->iw2btar, in pci_mcf547x_8x_init()
[all …]
/external/u-boot/arch/m68k/cpu/mcf52x2/
Dcpu_init.c39 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); in init_fbcs()
40 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); in init_fbcs()
41 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); in init_fbcs()
47 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); in init_fbcs()
48 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); in init_fbcs()
49 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); in init_fbcs()
53 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); in init_fbcs()
54 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); in init_fbcs()
55 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); in init_fbcs()
59 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); in init_fbcs()
[all …]
/external/u-boot/board/freescale/ls1021aiot/
Dls1021aiot.c52 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
54 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
55 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
57 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
58 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); in ddrmc_init()
59 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
60 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); in ddrmc_init()
61 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
62 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
64 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); in ddrmc_init()
[all …]
/external/u-boot/arch/m68k/cpu/mcf5445x/
Dpci.c31 out_be32(hose->cfg_addr, addr); \
33 out_be32(hose->cfg_addr, addr & 0x7fffffff); \
51 out_be32(&pciarb->acr, 0x001f001f); in pci_mcf5445x_init()
67 out_be32(&pci->iw0btar, in pci_mcf5445x_init()
69 out_be32(&pci->iw1btar, in pci_mcf5445x_init()
71 out_be32(&pci->iw2btar, in pci_mcf5445x_init()
74 out_be32(&pci->iwcr, in pci_mcf5445x_init()
78 out_be32(&pci->icr, 0); in pci_mcf5445x_init()
81 out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); in pci_mcf5445x_init()
84 out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8)); in pci_mcf5445x_init()
[all …]
/external/u-boot/board/gdsys/mpc8308/
Dsdram.c36 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
38 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); in fixed_sdram()
39 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
41 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
42 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
45 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
47 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
48 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
49 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
50 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
[all …]
/external/u-boot/board/freescale/mpc8308rdb/
Dsdram.c35 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
37 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); in fixed_sdram()
38 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
40 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
41 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
44 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
46 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
47 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
48 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
49 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
[all …]
/external/u-boot/board/mpc8308_p1m/
Dsdram.c31 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
33 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); in fixed_sdram()
34 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
36 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
37 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
40 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
42 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
43 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
44 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
45 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
[all …]
/external/u-boot/board/ve8313/
Dve8313.c40 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
42 out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); in fixed_sdram()
43 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
54 out_be32(&im->ddr.csbnds[0].csbnds, in fixed_sdram()
58 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
61 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
63 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); in fixed_sdram()
64 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
65 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
66 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
[all …]
/external/u-boot/board/ids/ids8313/
Dids8313.c59 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
61 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); in fixed_sdram()
62 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
71 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
72 out_be32(&im->ddr.cs_config[0], config); in fixed_sdram()
75 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
76 out_be32(&im->ddr.cs_config[2], 0); in fixed_sdram()
77 out_be32(&im->ddr.cs_config[3], 0); in fixed_sdram()
79 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
80 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dserdes.c55 out_be32(regs + FSL_SRDSCR0_OFFS, tmp); in fsl_setup_serdes()
60 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); in fsl_setup_serdes()
69 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); in fsl_setup_serdes()
72 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); in fsl_setup_serdes()
82 out_be32(regs + FSL_SRDSCR1_OFFS, tmp); in fsl_setup_serdes()
88 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); in fsl_setup_serdes()
94 out_be32(regs + FSL_SRDSCR3_OFFS, tmp); in fsl_setup_serdes()
98 out_be32(regs + FSL_SRDSCR4_OFFS, tmp); in fsl_setup_serdes()
105 out_be32(regs + FSL_SRDSCR1_OFFS, tmp); in fsl_setup_serdes()
111 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); in fsl_setup_serdes()
[all …]
/external/u-boot/drivers/net/fm/
Dfm.c81 out_be32(&imem->iadd, IRAM_IADD_AIE); in fm_upload_ucode()
84 out_be32(&imem->idata, (be32_to_cpu(ucode[i]))); in fm_upload_ucode()
87 out_be32(&imem->iadd, 0); in fm_upload_ucode()
94 out_be32(&imem->iready, IRAM_READY); in fm_upload_ucode()
221 out_be32(&fpm->fpmprc, val); in fm_init_fpm()
227 out_be32(&fpm->fpmprc, val); in fm_init_fpm()
233 out_be32(&fpm->fpmprc, val); in fm_init_fpm()
238 out_be32(&fpm->fpmprc, val); in fm_init_fpm()
242 out_be32(&fpm->fpmprc, val); in fm_init_fpm()
245 out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE); in fm_init_fpm()
[all …]
/external/u-boot/board/freescale/mpc8569mds/
Dmpc8569mds.c238 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); in fixed_sdram()
239 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
240 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
241 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
242 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
243 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
244 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
245 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); in fixed_sdram()
246 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); in fixed_sdram()
247 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); in fixed_sdram()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc8xxx/
Dsrio.c179 out_be32((void *)&srio_regs->impl.port[port].slcsr, in srio_erratum_a004034()
215 out_be32(((void *)&srio_regs->lp_serial in srio_erratum_a004034()
217 out_be32(((void *)&srio_regs->phys_err in srio_erratum_a004034()
219 out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0); in srio_erratum_a004034()
294 out_be32((void *)&srio->impl.port[port - 1].ptaacr, in srio_boot_master()
304 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar, in srio_boot_master()
306 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar, in srio_boot_master()
308 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar, in srio_boot_master()
318 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar, in srio_boot_master()
320 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar, in srio_boot_master()
[all …]
/external/u-boot/board/freescale/m547xevb/
Dm547xevb.c34 out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH); in dram_init()
42 out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
52 out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); in dram_init()
55 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
56 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
59 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
62 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
63 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
68 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
71 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/external/u-boot/board/freescale/m548xevb/
Dm548xevb.c34 out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH); in dram_init()
42 out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
52 out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); in dram_init()
55 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
56 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
59 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
62 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
63 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
68 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
71 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]

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