| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_rk322x.c | 27 struct rk322x_ddr_pctl *pctl; member
153 static void send_command(struct rk322x_ddr_pctl *pctl, in send_command() argument
156 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
158 while (readl(&pctl->mcmd) & START_CMD) in send_command()
165 struct rk322x_ddr_pctl *pctl = chan->pctl; in memory_init() local
169 send_command(pctl, 3, DESELECT_CMD, 0); in memory_init()
171 send_command(pctl, 3, PREA_CMD, 0); in memory_init()
172 send_command(pctl, 3, MRS_CMD, in memory_init()
177 send_command(pctl, 3, MRS_CMD, in memory_init()
182 send_command(pctl, 3, MRS_CMD, in memory_init()
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| D | dmc-rk3368.c | 27 struct rk3368_ddr_pctl *pctl; member
192 static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd) in send_command() argument
197 writel(mcmd, &pctl->mcmd); in send_command()
198 while (readl(&pctl->mcmd) & START_CMD) in send_command()
202 static void send_mrs(struct rk3368_ddr_pctl *pctl, in send_mrs() argument
208 writel(mcmd, &pctl->mcmd); in send_mrs()
209 while (readl(&pctl->mcmd) & START_CMD) in send_mrs()
213 static int memory_init(struct rk3368_ddr_pctl *pctl, in memory_init() argument
225 writel(POWER_UP_START, &pctl->powctl); in memory_init()
234 } while (!(readl(&pctl->powstat) & POWER_UP_DONE)); in memory_init()
[all …]
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| D | sdram_rk3288.c | 30 struct rk3288_ddr_pctl *pctl; member
171 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
173 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
175 &pctl->dfistcfg1); in dfi_cfg()
176 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
178 &pctl->dfilpcfg0); in dfi_cfg()
180 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
181 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
182 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
183 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
[all …]
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| D | sdram_rk3188.c | 28 struct rk3288_ddr_pctl *pctl; member
172 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
174 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
176 &pctl->dfistcfg1); in dfi_cfg()
177 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
179 &pctl->dfilpcfg0); in dfi_cfg()
181 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
182 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
183 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
184 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
[all …]
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| D | sdram_rk3399.c | 26 struct rk3399_ddr_pctl_regs *pctl; member
116 u32 *denali_ctl = chan->pctl->denali_ctl; in set_memory_map()
458 u32 *denali_ctl = chan->pctl->denali_ctl; in pctl_cfg()
584 u32 *denali_ctl = chan->pctl->denali_ctl; in override_write_leveling_value()
976 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], in dram_all_config()
1148 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk3399_dmc_init()
1152 priv->chan[1].pctl = regmap_get_range(plat->map, 4); in rk3399_dmc_init()
1158 priv->chan[0].pctl, priv->chan[0].pi, in rk3399_dmc_init()
1160 priv->chan[1].pctl, priv->chan[1].pi, in rk3399_dmc_init()
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| /external/u-boot/arch/arm/mach-rockchip/rk3036/ |
| D | sdram_rk3036.c | 29 struct rk3036_ddr_pctl *pctl; member
443 static void send_command(struct rk3036_ddr_pctl *pctl, in send_command() argument
446 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
448 while (readl(&pctl->mcmd) & START_CMD) in send_command()
454 struct rk3036_ddr_pctl *pctl = priv->pctl; in memory_init() local
456 send_command(pctl, 3, DESELECT_CMD, 0); in memory_init()
458 send_command(pctl, 3, PREA_CMD, 0); in memory_init()
459 send_command(pctl, 3, MRS_CMD, in memory_init()
464 send_command(pctl, 3, MRS_CMD, in memory_init()
469 send_command(pctl, 3, MRS_CMD, in memory_init()
[all …]
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| /external/grpc-grpc/tools/run_tests/performance/ |
| D | massage_qps_stats_helpers.py | 40 def percentile(buckets, pctl, boundaries): argument
42 sum(buckets) * pctl / 100.0)
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| /external/grpc-grpc/tools/codegen/core/ |
| D | gen_stats_data.py | 411 for pctl in RECORD_EXPLICIT_PERCENTILES:
413 'name': 'core_%s_%dp' % (histogram.name, pctl),
460 for pctl in RECORD_EXPLICIT_PERCENTILES:
462 histogram.name, pctl, pctl)
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| /external/u-boot/arch/arm/dts/ |
| D | rk3288-vyasa-u-boot.dtsi | 7 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
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| D | rk3288-miqi.dts | 19 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
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| D | rk3288-evb.dts | 19 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
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| D | rk3288-fennec.dts | 19 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
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| D | rk3288-popmetal.dts | 19 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
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| D | rk3288-tinker.dts | 19 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
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| D | rk3288-firefly.dts | 24 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
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| D | rk3229-evb.dts | 42 rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
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| D | rk3288-veyron-jerry.dts | 58 rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
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| D | rk3288-rock2-square.dts | 187 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
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| D | rk3188-radxarock.dts | 134 rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
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| D | rk3288-veyron-minnie.dts | 129 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
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| D | rk3288-phycore-rdk.dts | 122 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
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| D | rk3288-veyron-mickey.dts | 165 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | rockchip,rk3288-dmc.txt | 53 -rockchip,pctl-timing: parameters for the SDRAM setup, in this order:
146 rockchip,pctl-timing = <0x29a 0x1f4 0xc8 0x42 0x4e 0x4 0xea 0xa
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| /external/pcre/dist2/src/ |
| D | pcre2test.c | 3489 check_modifier(modstruct *m, int ctx, patctl *pctl, datctl *dctl, uint32_t c) in check_modifier() argument
3525 if (pctl != NULL) field = pctl; in check_modifier()
3533 else if (pctl != NULL && (m->which == MOD_PD || m->which == MOD_PDP || in check_modifier()
3535 field = pctl; in check_modifier()
3576 decode_modifiers(uint8_t *p, int ctx, patctl *pctl, datctl *dctl) in decode_modifiers() argument
3667 field = check_modifier(modlist + index, ctx, pctl, dctl, *p); in decode_modifiers()
3717 field = check_modifier(m, ctx, pctl, dctl, 0); in decode_modifiers()
3738 if (ctx == CTX_PAT || ctx == CTX_DEFPAT) pctl->control2 &= ~CTL2_BSR_SET; in decode_modifiers()
3748 if (ctx == CTX_PAT || ctx == CTX_DEFPAT) pctl->control2 |= CTL2_BSR_SET; in decode_modifiers()
3842 if (ctx == CTX_PAT || ctx == CTX_DEFPAT) pctl->control2 &= ~CTL2_NL_SET; in decode_modifiers()
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