| /external/u-boot/arch/arm/mach-imx/mx5/ |
| D | clock.c | 235 u32 ccsr = readl(&mxc_ccm->ccsr); in get_lp_apm() local
237 if (ccsr & MXC_CCM_CCSR_LP_APM) in get_lp_apm()
647 u32 ccsr = readl(&mxc_ccm->ccsr); in config_pll_clk() local
653 writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL, in config_pll_clk()
654 &mxc_ccm->ccsr); in config_pll_clk()
659 writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL, in config_pll_clk()
660 &mxc_ccm->ccsr); in config_pll_clk()
664 writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL, in config_pll_clk()
665 &mxc_ccm->ccsr); in config_pll_clk()
670 writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL, in config_pll_clk()
[all …]
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| /external/u-boot/drivers/pci/ |
| D | pcie_layerscape_gen4.h | 182 void __iomem *ccsr; member
218 val = in_le32(pcie->ccsr + PAB_CTRL); in ccsr_set_page()
222 out_le32(pcie->ccsr + PAB_CTRL, val); in ccsr_set_page()
229 return in_le32(pcie->ccsr + offset); in ccsr_readl()
233 return in_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset)); in ccsr_readl()
240 out_le32(pcie->ccsr + offset, value); in ccsr_writel()
243 out_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset), value); in ccsr_writel()
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| D | pcie_layerscape_gen4.c | 214 return pcie->ccsr + offset; in ls_pcie_g4_conf_address()
218 return pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset); in ls_pcie_g4_conf_address()
478 pcie->ccsr = map_physmem(pcie->ccsr_res.start, in ls_pcie_g4_probe()
518 dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg, in ls_pcie_g4_probe()
521 pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f; in ls_pcie_g4_probe()
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| /external/u-boot/arch/arm/dts/ |
| D | fsl-lx2160a.dtsi | 271 reg-names = "ccsr", "lut", "pf_ctrl", "config";
285 reg-names = "ccsr", "lut", "pf_ctrl", "config";
300 reg-names = "ccsr", "lut", "pf_ctrl", "config";
314 reg-names = "ccsr", "lut", "pf_ctrl", "config";
328 reg-names = "ccsr", "lut", "pf_ctrl", "config";
342 reg-names = "ccsr", "lut", "pf_ctrl", "config";
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| D | fsl-ls1012a.dtsi | 139 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
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| D | fsl-ls1088a.dtsi | 188 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
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| D | fsl-ls1043a.dtsi | 293 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
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| D | fsl-ls1028a.dtsi | 310 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
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| D | fsl-ls1046a.dtsi | 297 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
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| /external/u-boot/arch/arm/include/asm/arch-armada100/ |
| D | cpu.h | 45 u32 ccsr; /* 0x00C */ member
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| /external/u-boot/board/armadeus/apf27/ |
| D | fpga.c | 198 writel(ACFG_CCSR_VAL, &pll->ccsr); in apf27_fpga_setup()
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| /external/u-boot/arch/arm/mach-imx/mx6/ |
| D | clock.c | 1439 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1441 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1466 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1468 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
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| /external/u-boot/arch/arm/include/asm/arch-vf610/ |
| D | crm_regs.h | 17 u32 ccsr; member
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| /external/u-boot/arch/arm/cpu/armv7/vf610/ |
| D | generic.c | 47 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
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| /external/u-boot/board/phytec/pcm052/ |
| D | pcm052.c | 250 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, in clock_init()
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| /external/u-boot/board/toradex/colibri_vf/ |
| D | colibri_vf.c | 332 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | in clock_init()
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| /external/u-boot/board/freescale/vf610twr/ |
| D | vf610twr.c | 303 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, in clock_init()
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| /external/u-boot/arch/arm/lib/ |
| D | asm-offsets.c | 155 DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); in main()
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| /external/u-boot/arch/arm/include/asm/arch-mx27/ |
| D | imx-regs.h | 125 u32 ccsr; /* Clock Control Status Register */ member
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| /external/u-boot/arch/arm/include/asm/arch-mx5/ |
| D | imx-regs.h | 304 u32 ccsr; member
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| D | crm_regs.h | 32 u32 ccsr; member
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| /external/u-boot/arch/arm/include/asm/arch-mx6/ |
| D | crm_regs.h | 25 u32 ccsr; member
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