| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixupVectorISel.cpp | 87 unsigned &IndexReg, in findSRegBaseAndIndex() argument
118 IndexReg = DefInst->getOperand(3).getReg(); in findSRegBaseAndIndex()
120 MachineInstr *MI = MRI.getUniqueVRegDef(IndexReg); in findSRegBaseAndIndex()
130 IndexReg = MI->getOperand(1).getReg(); in findSRegBaseAndIndex()
143 if (!TRI->hasVGPRs(MRI.getRegClass(IndexReg))) in findSRegBaseAndIndex()
146 MRI.clearKillFlags(IndexReg); in findSRegBaseAndIndex()
176 unsigned IndexReg = 0; in fixupGlobalSaddr() local
178 if (!findSRegBaseAndIndex(Op, BaseReg, IndexReg, MRI, TRI)) in fixupGlobalSaddr()
189 NewGlob->addOperand(MF, MachineOperand::CreateReg(IndexReg, false)); in fixupGlobalSaddr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 369 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
379 if (IndexReg != 0) in optTwoAddrLEA()
380 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optTwoAddrLEA()
387 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
388 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
391 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
396 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
401 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
403 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
549 Register IndexReg = Index.getReg(); in processInstrForSlow3OpLEA() local
[all …]
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| D | X86InstrBuilder.h | 54 unsigned IndexReg; member
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
108 AM.IndexReg = Op2.getReg(); in getAddressFromInstr()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
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| D | X86InsertPrefetch.cpp | 83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
87 (IndexReg == 0 || in IsMemOpCompatibleWithPrefetch()
88 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) || in IsMemOpCompatibleWithPrefetch()
89 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)); in IsMemOpCompatibleWithPrefetch()
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| D | X86AsmPrinter.cpp | 286 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
296 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
317 assert(IndexReg.getReg() != X86::ESP && in PrintLeaMemReference()
324 if (IndexReg.getReg()) { in PrintLeaMemReference()
352 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
376 if (IndexReg.getReg()) { in PrintIntelMemReference()
389 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 385 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
395 if (IndexReg != 0) in optTwoAddrLEA()
396 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optTwoAddrLEA()
403 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
404 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
407 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
412 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
417 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
419 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
570 Register IndexReg = Index.getReg(); in processInstrForSlow3OpLEA() local
[all …]
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| D | X86InstrBuilder.h | 54 unsigned IndexReg; member
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
108 AM.IndexReg = Op2.getReg(); in getAddressFromInstr()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
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| D | X86InsertPrefetch.cpp | 83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
87 (IndexReg == 0 || in IsMemOpCompatibleWithPrefetch()
88 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) || in IsMemOpCompatibleWithPrefetch()
89 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)); in IsMemOpCompatibleWithPrefetch()
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| D | X86AsmPrinter.cpp | 289 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
299 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
320 assert(IndexReg.getReg() != X86::ESP && in PrintLeaMemReference()
327 if (IndexReg.getReg()) { in PrintLeaMemReference()
355 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
379 if (IndexReg.getReg()) { in PrintIntelMemReference()
392 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 345 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon7e5fbfb70111::X86AsmParser::IntelExprStateMachine
368 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), in IntelExprStateMachine()
378 unsigned getIndexReg() { return IndexReg; } in getIndexReg()
482 if (IndexReg) { in onPlus()
486 IndexReg = TmpReg; in onPlus()
537 if (IndexReg) { in onMinus()
541 IndexReg = TmpReg; in onMinus()
592 if (IndexReg) { in onRegister()
597 IndexReg = Reg; in onRegister()
666 if (IndexReg) { in onInteger()
[all …]
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| D | X86Operand.h | 63 unsigned IndexReg; member
137 if (Mem.IndexReg) in print()
139 << X86IntelInstPrinter::getRegisterName(Mem.IndexReg); in print()
189 return Mem.IndexReg; in getMemIndexReg()
317 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
636 Res->Mem.IndexReg = 0;
650 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
655 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
664 Res->Mem.IndexReg = IndexReg;
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 49 unsigned IndexReg; member
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
104 AM.IndexReg = Op.getImm(); in getAddressFromInstr()
162 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
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| D | X86AsmPrinter.cpp | 232 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printLeaMemReference() local
242 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
262 assert(IndexReg.getReg() != X86::ESP && in printLeaMemReference()
269 if (IndexReg.getReg()) { in printLeaMemReference()
298 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printIntelMemReference() local
316 if (IndexReg.getReg()) { in printIntelMemReference()
329 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printIntelMemReference()
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| D | X86ISelDAGToDAG.cpp | 62 SDValue IndexReg; member
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
114 if (IndexReg.getNode()) in dump()
115 IndexReg.getNode()->dump(); in dump()
254 Index = AM.IndexReg; in getAddressOperands()
847 AM.Base_Reg = AM.IndexReg; in matchAddress()
859 AM.IndexReg.getNode() == nullptr && in matchAddress()
890 !AM.IndexReg.getNode()) { in matchAdd()
893 AM.IndexReg = N.getOperand(1); in matchAdd()
[all …]
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| /external/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 426 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anona5c84dc30111::X86AsmParser::IntelExprStateMachine
450 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), in IntelExprStateMachine()
460 unsigned getIndexReg() const { return IndexReg; } in getIndexReg()
658 if (IndexReg) { in onPlus()
662 IndexReg = TmpReg; in onPlus()
719 if (IndexReg) { in onMinus()
723 IndexReg = TmpReg; in onMinus()
780 if (IndexReg) { in onRegister()
785 IndexReg = Reg; in onRegister()
864 if (IndexReg) { in onInteger()
[all …]
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| D | X86Operand.h | 62 unsigned IndexReg; member
136 if (Mem.IndexReg) in print()
138 << X86IntelInstPrinter::getRegisterName(Mem.IndexReg); in print()
192 return Mem.IndexReg; in getMemIndexReg()
325 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
672 Res->Mem.IndexReg = 0;
686 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
693 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
704 Res->Mem.IndexReg = IndexReg;
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anond14900950111::X86AsmParser::IntelExprStateMachine
274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
279 unsigned getIndexReg() { return IndexReg; } in getIndexReg()
387 assert (!IndexReg && "BaseReg/IndexReg already set!"); in onPlus()
388 IndexReg = TmpReg; in onPlus()
424 assert (!IndexReg && "BaseReg/IndexReg already set!"); in onMinus()
425 IndexReg = TmpReg; in onMinus()
461 assert (!IndexReg && "IndexReg already set!"); in onRegister()
463 IndexReg = Reg; in onRegister()
511 assert (!IndexReg && "IndexReg already set!"); in onInteger()
[all …]
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| D | X86Operand.h | 56 unsigned IndexReg; member
121 return Mem.IndexReg; in getMemIndexReg()
238 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
504 Res->Mem.IndexReg = 0;
517 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
522 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
531 Res->Mem.IndexReg = IndexReg;
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is16BitMemOperand() local
69 (IndexReg.getReg() != 0 && in Is16BitMemOperand()
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) in Is16BitMemOperand()
207 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand() local
211 (IndexReg.getReg() != 0 && in Is32BitMemOperand()
212 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in Is32BitMemOperand()
215 assert(IndexReg.getReg() == 0 && "Invalid eip-based address."); in Is32BitMemOperand()
226 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is64BitMemOperand() local
230 (IndexReg.getReg() != 0 && in Is64BitMemOperand()
231 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) in Is64BitMemOperand()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 187 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand() local
195 (IndexReg.getReg() != 0 && in is16BitMemOperand()
196 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) in is16BitMemOperand()
206 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand() local
210 (IndexReg.getReg() != 0 && in is32BitMemOperand()
211 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in is32BitMemOperand()
214 assert(IndexReg.getReg() == 0 && "Invalid eip-based address."); in is32BitMemOperand()
217 if (IndexReg.getReg() == X86::EIZ) in is32BitMemOperand()
228 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is64BitMemOperand() local
232 (IndexReg.getReg() != 0 && in is64BitMemOperand()
[all …]
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| /external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 166 unsigned IndexReg = Index.getReg(); in is16BitMemOperand() local
168 if (STI.hasFeature(X86::Mode16Bit) && BaseReg == 0 && IndexReg == 0) in is16BitMemOperand()
172 (IndexReg != 0 && in is16BitMemOperand()
173 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))) in is16BitMemOperand()
183 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand() local
187 (IndexReg.getReg() != 0 && in is32BitMemOperand()
188 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in is32BitMemOperand()
191 assert(IndexReg.getReg() == 0 && "Invalid eip-based address."); in is32BitMemOperand()
194 if (IndexReg.getReg() == X86::EIZ) in is32BitMemOperand()
205 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is64BitMemOperand() local
[all …]
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 198 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
212 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
219 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
224 if (IndexReg.getReg()) { in printMemReference()
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| D | X86IntelInstPrinter.cpp | 161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
179 if (IndexReg.getReg()) { in printMemReference()
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
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| /external/llvm-project/llvm/include/llvm/MC/MCParser/ |
| D | MCTargetAsmParser.h | 67 StringRef IndexReg; member
72 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()), in IntelExpr()
77 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
83 bool hasIndexReg() const { return !IndexReg.empty(); } in hasIndexReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/MCParser/ |
| D | MCTargetAsmParser.h | 68 StringRef IndexReg; member
73 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()), in IntelExpr()
78 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
84 bool hasIndexReg() const { return !IndexReg.empty(); } in hasIndexReg()
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