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Searched refs:ZEXTLOAD (Results 1 – 25 of 130) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-zextload-global.mir24 ; GFX8: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
25 ; GFX8: $vgpr0 = COPY [[ZEXTLOAD]](s32)
28 ; GFX6: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
29 ; GFX6: $vgpr0 = COPY [[ZEXTLOAD]](s32)
42 ; GFX8: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 2, addrspace 1)
43 ; GFX8: $vgpr0 = COPY [[ZEXTLOAD]](s32)
46 ; GFX6: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 2, addrspace 1)
47 ; GFX6: $vgpr0 = COPY [[ZEXTLOAD]](s32)
60 ; GFX8: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
61 ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
[all …]
Dlegalize-zextload-private.mir13 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 1, addrspace 5)
14 ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
27 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 2, addrspace 5)
28 ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
41 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 1, addrspace 5)
42 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
57 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 1, addrspace 5)
58 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
72 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 2, addrspace 5)
73 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
Dlegalize-zextload-local.mir12 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 1, addrspace 3)
13 ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
26 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 2, addrspace 3)
27 ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
40 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 1, addrspace 3)
41 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
56 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 1, addrspace 3)
57 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
71 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 2, addrspace 3)
72 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
Dlegalize-zextload-flat.mir12 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
13 ; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
33 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
34 ; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
54 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
55 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
78 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
79 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
101 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
102 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
Dregbankselect-zextload.mir15 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 4)
31 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 1)
47 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 4)
63 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 1)
78 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p3) :: (load 1, addrspace 3)
94 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p3) :: (load 2, addrspace 3)
Dcombine-sext-inreg.mir197 ; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
198 ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ZEXTLOAD]], 7
217 ; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
218 ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ZEXTLOAD]], 8
237 ; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
238 ; GCN: $vgpr0 = COPY [[ZEXTLOAD]](s32)
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/
DzextLoad_and_sextLoad.mir28 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
29 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
49 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
50 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
70 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s16) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
71 ; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXTLOAD]](s16)
93 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
94 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
115 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
116 ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXTLOAD]](s64)
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-extload.mir121 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.ptr)
122 ; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
138 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.ptr)
139 ; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
155 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.ptr)
156 ; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
Dlegalize-zextload.mir10 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
11 ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
Dpostlegalizercombiner-extending-loads.mir25 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.addr)
26 ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
Dlegalize-non-pow2-load-store.mir27 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.ptr, align 4)
33 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
DzextLoad_and_sextLoad.mir28 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
29 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
48 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
49 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
68 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
69 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
90 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
91 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
DzextLoad_and_sextLoad.mir25 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
26 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
46 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
47 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h1026 ZEXTLOAD enumerator
1029 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h1243 enum LoadExtType { NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD }; enumerator
1245 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h830 ZEXTLOAD, enumerator
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp687 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
719 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
756 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp103 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
115 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
116 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
117 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
118 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
129 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
135 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
DR600ISelLowering.cpp57 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
58 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
59 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
69 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
1592 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp663 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
695 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
84 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
85 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
95 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
99 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
1468 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
DAMDGPUISelLowering.cpp111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
123 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
143 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand); in AMDGPUTargetLowering()
149 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
84 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
85 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
95 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
99 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
1474 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp251 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
306 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
482 IntExt = ISD::ZEXTLOAD; in tryLoadOfLoadIntrinsic()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp961 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteOperand()
1186 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteLoad()
3021 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { in isAndLoadExtLoad()
3038 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT)) in isAndLoadExtLoad()
3041 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) in isAndLoadExtLoad()
3183 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, in visitAND()
3197 case ISD::ZEXTLOAD: in visitAND()
3206 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, in visitAND()
3249 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
3277 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
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