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/external/llvm-project/llvm/test/MC/RISCV/rvv/
Dconvert.s59 vfcvt.rtz.xu.f.v v8, v4, v0.t
60 # CHECK-INST: vfcvt.rtz.xu.f.v v8, v4, v0.t
65 vfcvt.rtz.xu.f.v v8, v4
66 # CHECK-INST: vfcvt.rtz.xu.f.v v8, v4
71 vfcvt.rtz.x.f.v v8, v4, v0.t
72 # CHECK-INST: vfcvt.rtz.x.f.v v8, v4, v0.t
77 vfcvt.rtz.x.f.v v8, v4
78 # CHECK-INST: vfcvt.rtz.x.f.v v8, v4
143 vfwcvt.rtz.xu.f.v v8, v4, v0.t
144 # CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4, v0.t
[all …]
/external/llvm-project/llvm/test/CodeGen/RISCV/
Dhalf-convert.ll14 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
19 ; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
24 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
29 ; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
38 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
43 ; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
48 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
53 ; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
62 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
67 ; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
[all …]
Drv64d-double-convert.ll14 ; RV64ID-NEXT: fcvt.l.d a0, ft0, rtz
24 ; RV64ID-NEXT: fcvt.l.d a0, ft0, rtz
34 ; RV64ID-NEXT: fcvt.l.d a0, ft0, rtz
46 ; RV64ID-NEXT: fcvt.lu.d a0, ft0, rtz
56 ; RV64ID-NEXT: fcvt.wu.d a0, ft0, rtz
66 ; RV64ID-NEXT: fcvt.lu.d a0, ft0, rtz
Drv64f-half-convert.ll13 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
22 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
31 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
42 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
51 ; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
60 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
Drv64f-float-convert.ll14 ; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
24 ; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
34 ; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
46 ; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
56 ; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
66 ; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
Dfloat-convert.ll13 ; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
19 ; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
31 ; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz
37 ; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
133 ; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
152 ; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
Ddouble-convert.ll60 ; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
67 ; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
82 ; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
89 ; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
148 ; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
167 ; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
Dcalling-conv-ilp32f-ilp32d-common.ll15 ; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
44 ; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
83 ; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa7, rtz
84 ; RV32-ILP32FD-NEXT: fcvt.w.s a1, ft0, rtz
130 ; RV32-ILP32FD-NEXT: fcvt.w.s a0, ft0, rtz
Dcalling-conv-ilp32d.ll12 ; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz
41 ; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz
83 ; RV32-ILP32D-NEXT: fcvt.w.d a0, fa7, rtz
84 ; RV32-ILP32D-NEXT: fcvt.w.d a1, ft0, rtz
136 ; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz
192 ; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz
/external/llvm-project/llvm/test/MC/RISCV/
Drv32f-valid.s123 # CHECK-ASM-AND-OBJ: fmsub.s fa4, fa5, fa6, fa7, rtz
125 fmsub.s f14, f15, f16, f17, rtz
142 # CHECK-ASM-AND-OBJ: fsub.s ft9, ft10, ft11, rtz
144 fsub.s f29, f30, f31, rtz
161 # CHECK-ASM-AND-OBJ: fcvt.s.w ft11, a4, rtz
163 fcvt.s.w ft11, a4, rtz
Drv32zfh-valid.s123 # CHECK-ASM-AND-OBJ: fmsub.h fa4, fa5, fa6, fa7, rtz
125 fmsub.h f14, f15, f16, f17, rtz
142 # CHECK-ASM-AND-OBJ: fsub.h ft9, ft10, ft11, rtz
144 fsub.h f29, f30, f31, rtz
161 # CHECK-ASM-AND-OBJ: fcvt.h.w ft11, a4, rtz
163 fcvt.h.w ft11, a4, rtz
Drv64f-valid.s31 # CHECK-ASM-AND-OBJ: fcvt.lu.s a5, ft5, rtz
33 fcvt.lu.s a5, ft5, rtz
Drv64zfh-valid.s31 # CHECK-ASM-AND-OBJ: fcvt.lu.h a5, ft5, rtz
33 fcvt.lu.h a5, ft5, rtz
Drv32d-valid.s127 # CHECK-ASM-AND-OBJ: fmsub.d fa4, fa5, fa6, fa7, rtz
129 fmsub.d f14, f15, f16, f17, rtz
146 # CHECK-ASM-AND-OBJ: fdiv.d ft3, ft4, ft5, rtz
148 fdiv.d ft3, ft4, ft5, rtz
Drv64d-valid.s40 # CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, rtz
43 fcvt.d.lu ft4, a4, rtz
/external/mesa3d/src/util/
Dsoftfloat.h58 float _mesa_double_to_f32(double x, bool rtz);
Dsoftfloat.c175 float _mesa_round_f32(int32_t s, int32_t e, int32_t m, bool rtz) in _mesa_round_f32() argument
178 uint8_t round_increment = rtz ? 0 : 0x40; in _mesa_round_f32()
196 m &= ~(uint32_t) (! (round_bits ^ 0x40) & !rtz); in _mesa_round_f32()
1384 _mesa_double_to_f32(double val, bool rtz) in _mesa_double_to_f32() argument
1428 return _mesa_round_f32(s, flt_e - 0x381, m | 0x40000000, rtz); in _mesa_double_to_f32()
/external/OpenCL-CTS/test_conformance/spirv_new/
Dtest_decorate.cpp429 TEST_SPIRV_FP_ROUNDING_DECORATE(rtz, round_to_zero, float, int);
434 TEST_SPIRV_FP_ROUNDING_DECORATE(rtz, round_to_zero, double, long);
/external/elfutils/tests/
Dtestfile-riscv64-dis1.expect.bz21testfile-riscv64-dis1.o: elf64-elf_riscv 2 3Disassembly of section .text ...
/external/mesa3d/docs/relnotes/
D20.1.7.rst147 - aco: fix non-rtz pack_half_2x16
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoV.td838 defm VFCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>;
839 defm VFCVT_RTZ_X_F_V : VALU_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>;
847 defm VFWCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>;
848 defm VFWCVT_RTZ_X_F_V : VALU_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>;
858 defm VFNCVT_RTZ_XU_F_W : VALU_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>;
859 defm VFNCVT_RTZ_X_F_W : VALU_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>;
/external/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td149 // and always uses rtz, so is not suitable for implementing the OpenCL
/external/deqp/external/vulkancts/modules/vulkan/spirv_assembly/
DvktSpvAsmFloatControlsTests.cpp3669 const string& rtz = m_behaviorToName.at(B_RTZ_ROUNDING); in fillShaderSpec() local
3671 fp16behaviorName = fp16RteRounding ? rte : rtz; in fillShaderSpec()
3672 fp32behaviorName = fp32RteRounding ? rte : rtz; in fillShaderSpec()
3673 fp64behaviorName = fp64RteRounding ? rte : rtz; in fillShaderSpec()
3682 "OpCapability " + rtz + "\n"; in fillShaderSpec()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dmode-register.mir4 # check that the mode is changed to rtz from default rtn for interp f16
/external/ImageMagick/PerlMagick/t/reference/write/read/
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