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Searched refs:s_not_b64 (Results 1 – 25 of 40) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.set.inactive.ll6 ; GCN: s_not_b64 exec, exec
8 ; GCN: s_not_b64 exec, exec
16 ; GCN: s_not_b64 exec, exec
19 ; GCN: s_not_b64 exec, exec
Dfix-wwm-vgpr-copy.ll23 ; GCN: s_not_b64 exec, exec
25 ; GCN: s_not_b64 exec, exec
Dsub_i1.ll18 ; WAVE64: s_not_b64
29 ; WAVE64: s_not_b64
Dadd_i1.ll17 ; GFX9: s_not_b64
28 ; GFX9: s_not_b64
Dxnor.ll48 ; GCN: s_not_b64
115 ; GCN: s_not_b64
134 ; GCN: s_not_b64
Datomic_optimizations_local_pointer.ll377 ; GFX8-NEXT: s_not_b64 exec, exec
379 ; GFX8-NEXT: s_not_b64 exec, exec
428 ; GFX9-NEXT: s_not_b64 exec, exec
430 ; GFX9-NEXT: s_not_b64 exec, exec
472 ; GFX1064-NEXT: s_not_b64 exec, exec
474 ; GFX1064-NEXT: s_not_b64 exec, exec
616 ; GFX8-NEXT: s_not_b64 exec, exec
618 ; GFX8-NEXT: s_not_b64 exec, exec
667 ; GFX9-NEXT: s_not_b64 exec, exec
669 ; GFX9-NEXT: s_not_b64 exec, exec
[all …]
Dwwm-reserved.ll106 ; GFX9-NEXT: s_not_b64 exec, exec
109 ; GFX9-NEXT: s_not_b64 exec, exec
144 ; GFX9: s_not_b64 exec, exec
149 ; GFX9-NEXT: s_not_b64 exec, exec
Datomic_optimizations_pixelshader.ll220 ; GFX8-NEXT: s_not_b64 exec, exec
222 ; GFX8-NEXT: s_not_b64 exec, exec
275 ; GFX9-NEXT: s_not_b64 exec, exec
277 ; GFX9-NEXT: s_not_b64 exec, exec
325 ; GFX1064-NEXT: s_not_b64 exec, exec
327 ; GFX1064-NEXT: s_not_b64 exec, exec
Dnor.ll47 ; GCN: s_not_b64
Dnand.ll47 ; GCN: s_not_b64
Dxor.ll132 ; SI: s_not_b64
Dwave32.ll626 ; GFX1064: s_not_b64 exec, exec{{$}}
628 ; GFX1064: s_not_b64 exec, exec{{$}}
640 ; GFX1064: s_not_b64 exec, exec{{$}}
643 ; GFX1064: s_not_b64 exec, exec{{$}}
Dwqm.ll336 ;CHECK: s_not_b64 exec, exec
338 ;CHECK: s_not_b64 exec, exec
/external/llvm/test/MC/AMDGPU/
Dsop1.s71 s_not_b64 s[2:3], s[4:5] label
/external/llvm-project/llvm/test/MC/AMDGPU/
Dreg-syntax-extra.s168 s_not_b64 s[2:3], null label
Dsop1.s96 s_not_b64 s[2:3], s[4:5] label
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dxnor.ll158 ; GCN-NEXT: s_not_b64 s[4:5], s[2:3]
343 ; GCN-NEXT: s_not_b64 s[2:3], s[2:3]
356 ; GCN-NEXT: s_not_b64 s[0:1], s[0:1]
Dorn2.ll125 ; GCN-NEXT: s_not_b64 s[6:7], s[4:5]
168 ; GCN-NEXT: s_not_b64 s[0:1], s[2:3]
Dandn2.ll125 ; GCN-NEXT: s_not_b64 s[6:7], s[4:5]
168 ; GCN-NEXT: s_not_b64 s[0:1], s[2:3]
/external/llvm/test/CodeGen/AMDGPU/
Dfceil64.ll18 ; SI-DAG: s_not_b64
Dftrunc.f64.ll30 ; SI-DAG: s_not_b64
Dxor.ll132 ; SI: s_not_b64
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt45 # VI: s_not_b64 s[2:3], s[4:5] ; encoding: [0x04,0x05,0x82,0xbe]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt54 # VI: s_not_b64 s[2:3], s[4:5] ; encoding: [0x04,0x05,0x82,0xbe]
/external/mesa3d/src/amd/compiler/
Daco_optimizer.cpp1408 case aco_opcode::s_not_b64: in label_instruction()
2185 …nstr || (op2_instr->opcode != aco_opcode::s_not_b32 && op2_instr->opcode != aco_opcode::s_not_b64)) in combine_salu_n2()
2887 } else if (instr->opcode == aco_opcode::s_not_b32 || instr->opcode == aco_opcode::s_not_b64) { in combine_instruction()

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